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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mattr=+enable-flat-scratch -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefix=MESA %s3; RUN: llc -global-isel -new-reg-bank-select -mattr=+enable-flat-scratch -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=PAL %s4 5; Test that the initialization for flat_scratch doesn't crash. PAL6; doesn't add a user SGPR for initializing flat_scratch, mesa does7; (although this probably isn't actually defined).8 9define amdgpu_ps void @amdgpu_ps() {10; MESA-LABEL: amdgpu_ps:11; MESA: ; %bb.0:12; MESA-NEXT: s_mov_b64 s[0:1], src_private_base13; MESA-NEXT: s_mov_b32 s0, 014; MESA-NEXT: s_add_u32 flat_scratch_lo, s2, s415; MESA-NEXT: v_mov_b32_e32 v0, s016; MESA-NEXT: s_addc_u32 flat_scratch_hi, s3, 017; MESA-NEXT: v_mov_b32_e32 v2, 018; MESA-NEXT: v_mov_b32_e32 v1, s119; MESA-NEXT: flat_store_dword v[0:1], v220; MESA-NEXT: s_waitcnt vmcnt(0)21; MESA-NEXT: s_endpgm22;23; PAL-LABEL: amdgpu_ps:24; PAL: ; %bb.0:25; PAL-NEXT: s_getpc_b64 s[2:3]26; PAL-NEXT: s_mov_b32 s2, s027; PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x028; PAL-NEXT: v_mov_b32_e32 v2, 029; PAL-NEXT: s_waitcnt lgkmcnt(0)30; PAL-NEXT: s_and_b32 s3, s3, 0xffff31; PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s032; PAL-NEXT: s_mov_b64 s[0:1], src_private_base33; PAL-NEXT: s_mov_b32 s0, 034; PAL-NEXT: v_mov_b32_e32 v0, s035; PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 036; PAL-NEXT: v_mov_b32_e32 v1, s137; PAL-NEXT: flat_store_dword v[0:1], v238; PAL-NEXT: s_waitcnt vmcnt(0)39; PAL-NEXT: s_endpgm40 %alloca = alloca i32, addrspace(5)41 %cast = addrspacecast ptr addrspace(5) %alloca to ptr42 store volatile i32 0, ptr %cast43 ret void44}45 46