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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GCN,GFX11 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GCN,GFX12 %s4 5define amdgpu_ps void @v_fneg_f16(half %in, ptr addrspace(1) %out) {6; GCN-LABEL: v_fneg_f16:7; GCN: ; %bb.0:8; GCN-NEXT: v_xor_b32_e32 v0, 0x8000, v09; GCN-NEXT: global_store_b16 v[1:2], v0, off10; GCN-NEXT: s_endpgm11 %fneg = fneg half %in12 store half %fneg, ptr addrspace(1) %out13 ret void14}15define amdgpu_ps void @s_fneg_f16(half inreg %in, ptr addrspace(1) %out) {16; GFX11-LABEL: s_fneg_f16:17; GFX11: ; %bb.0:18; GFX11-NEXT: v_xor_b32_e64 v2, 0x8000, s019; GFX11-NEXT: global_store_b16 v[0:1], v2, off20; GFX11-NEXT: s_endpgm21;22; GFX12-LABEL: s_fneg_f16:23; GFX12: ; %bb.0:24; GFX12-NEXT: s_xor_b32 s0, s0, 0x800025; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)26; GFX12-NEXT: v_mov_b32_e32 v2, s027; GFX12-NEXT: global_store_b16 v[0:1], v2, off28; GFX12-NEXT: s_endpgm29 %fneg = fneg half %in30 store half %fneg, ptr addrspace(1) %out31 ret void32}33define amdgpu_ps void @s_fneg_f16_salu_use(half inreg %in, i32 inreg %val, ptr addrspace(1) %out) {34; GFX11-LABEL: s_fneg_f16_salu_use:35; GFX11: ; %bb.0:36; GFX11-NEXT: v_xor_b32_e64 v2, 0x8000, s037; GFX11-NEXT: s_cmp_eq_u32 s1, 038; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)39; GFX11-NEXT: v_readfirstlane_b32 s0, v240; GFX11-NEXT: s_cselect_b32 s0, s0, 041; GFX11-NEXT: v_mov_b32_e32 v2, s042; GFX11-NEXT: global_store_b16 v[0:1], v2, off43; GFX11-NEXT: s_endpgm44;45; GFX12-LABEL: s_fneg_f16_salu_use:46; GFX12: ; %bb.0:47; GFX12-NEXT: s_xor_b32 s0, s0, 0x800048; GFX12-NEXT: s_cmp_eq_u32 s1, 049; GFX12-NEXT: s_cselect_b32 s0, s0, 050; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)51; GFX12-NEXT: v_mov_b32_e32 v2, s052; GFX12-NEXT: global_store_b16 v[0:1], v2, off53; GFX12-NEXT: s_endpgm54 %fneg = fneg half %in55 %cond = icmp eq i32 %val, 056 %sel = select i1 %cond, half %fneg, half 0.057 store half %sel, ptr addrspace(1) %out58 ret void59}60 61define amdgpu_ps void @v_fneg_f32(float %in, ptr addrspace(1) %out) {62; GCN-LABEL: v_fneg_f32:63; GCN: ; %bb.0:64; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v065; GCN-NEXT: global_store_b32 v[1:2], v0, off66; GCN-NEXT: s_endpgm67 %fneg = fneg float %in68 store float %fneg, ptr addrspace(1) %out69 ret void70}71define amdgpu_ps void @s_fneg_f32(float inreg %in, ptr addrspace(1) %out) {72; GFX11-LABEL: s_fneg_f32:73; GFX11: ; %bb.0:74; GFX11-NEXT: v_xor_b32_e64 v2, 0x80000000, s075; GFX11-NEXT: global_store_b32 v[0:1], v2, off76; GFX11-NEXT: s_endpgm77;78; GFX12-LABEL: s_fneg_f32:79; GFX12: ; %bb.0:80; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000000081; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)82; GFX12-NEXT: v_mov_b32_e32 v2, s083; GFX12-NEXT: global_store_b32 v[0:1], v2, off84; GFX12-NEXT: s_endpgm85 %fneg = fneg float %in86 store float %fneg, ptr addrspace(1) %out87 ret void88}89define amdgpu_ps void @s_fneg_f32_salu_use(float inreg %in, i32 inreg %val, ptr addrspace(1) %out) {90; GFX11-LABEL: s_fneg_f32_salu_use:91; GFX11: ; %bb.0:92; GFX11-NEXT: v_xor_b32_e64 v2, 0x80000000, s093; GFX11-NEXT: s_cmp_eq_u32 s1, 094; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)95; GFX11-NEXT: v_readfirstlane_b32 s0, v296; GFX11-NEXT: s_cselect_b32 s0, s0, 097; GFX11-NEXT: v_mov_b32_e32 v2, s098; GFX11-NEXT: global_store_b32 v[0:1], v2, off99; GFX11-NEXT: s_endpgm100;101; GFX12-LABEL: s_fneg_f32_salu_use:102; GFX12: ; %bb.0:103; GFX12-NEXT: s_xor_b32 s0, s0, 0x80000000104; GFX12-NEXT: s_cmp_eq_u32 s1, 0105; GFX12-NEXT: s_cselect_b32 s0, s0, 0106; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)107; GFX12-NEXT: v_mov_b32_e32 v2, s0108; GFX12-NEXT: global_store_b32 v[0:1], v2, off109; GFX12-NEXT: s_endpgm110 %fneg = fneg float %in111 %cond = icmp eq i32 %val, 0112 %sel = select i1 %cond, float %fneg, float 0.0113 store float %sel, ptr addrspace(1) %out114 ret void115}116 117define amdgpu_ps void @v_fneg_f64(double %in, ptr addrspace(1) %out) {118; GCN-LABEL: v_fneg_f64:119; GCN: ; %bb.0:120; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1121; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off122; GCN-NEXT: s_endpgm123 %fneg = fneg double %in124 store double %fneg, ptr addrspace(1) %out125 ret void126}127define amdgpu_ps void @s_fneg_f64(double inreg %in, ptr addrspace(1) %out) {128; GCN-LABEL: s_fneg_f64:129; GCN: ; %bb.0:130; GCN-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0131; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)132; GCN-NEXT: v_xor_b32_e32 v3, 0x80000000, v3133; GCN-NEXT: global_store_b64 v[0:1], v[2:3], off134; GCN-NEXT: s_endpgm135 %fneg = fneg double %in136 store double %fneg, ptr addrspace(1) %out137 ret void138}139define amdgpu_ps void @s_fneg_f64_salu_use(double inreg %in, i32 inreg %val, ptr addrspace(1) %out) {140; GFX11-LABEL: s_fneg_f64_salu_use:141; GFX11: ; %bb.0:142; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0143; GFX11-NEXT: s_cmp_eq_u32 s2, 0144; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)145; GFX11-NEXT: v_xor_b32_e32 v3, 0x80000000, v3146; GFX11-NEXT: v_readfirstlane_b32 s0, v2147; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)148; GFX11-NEXT: v_readfirstlane_b32 s1, v3149; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], 0150; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0151; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off152; GFX11-NEXT: s_endpgm153;154; GFX12-LABEL: s_fneg_f64_salu_use:155; GFX12: ; %bb.0:156; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0157; GFX12-NEXT: s_cmp_eq_u32 s2, 0158; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)159; GFX12-NEXT: v_xor_b32_e32 v3, 0x80000000, v3160; GFX12-NEXT: v_readfirstlane_b32 s0, v2161; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)162; GFX12-NEXT: v_readfirstlane_b32 s1, v3163; GFX12-NEXT: s_cselect_b64 s[0:1], s[0:1], 0164; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)165; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0166; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off167; GFX12-NEXT: s_endpgm168 %fneg = fneg double %in169 %cond = icmp eq i32 %val, 0170 %sel = select i1 %cond, double %fneg, double 0.0171 store double %sel, ptr addrspace(1) %out172 ret void173}174 175define amdgpu_ps void @v_fneg_v2f16(<2 x half> %in, ptr addrspace(1) %out) {176; GCN-LABEL: v_fneg_v2f16:177; GCN: ; %bb.0:178; GCN-NEXT: v_xor_b32_e32 v0, 0x80008000, v0179; GCN-NEXT: global_store_b32 v[1:2], v0, off180; GCN-NEXT: s_endpgm181 %fneg = fneg <2 x half> %in182 store <2 x half> %fneg, ptr addrspace(1) %out183 ret void184}185define amdgpu_ps void @s_fneg_v2f16(<2 x half> inreg %in, ptr addrspace(1) %out) {186; GFX11-LABEL: s_fneg_v2f16:187; GFX11: ; %bb.0:188; GFX11-NEXT: v_xor_b32_e64 v2, 0x80008000, s0189; GFX11-NEXT: global_store_b32 v[0:1], v2, off190; GFX11-NEXT: s_endpgm191;192; GFX12-LABEL: s_fneg_v2f16:193; GFX12: ; %bb.0:194; GFX12-NEXT: s_lshr_b32 s1, s0, 16195; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000196; GFX12-NEXT: s_xor_b32 s1, s1, 0x8000197; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)198; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1199; GFX12-NEXT: v_mov_b32_e32 v2, s0200; GFX12-NEXT: global_store_b32 v[0:1], v2, off201; GFX12-NEXT: s_endpgm202 %fneg = fneg <2 x half> %in203 store <2 x half> %fneg, ptr addrspace(1) %out204 ret void205}206define amdgpu_ps void @s_fneg_v2f16_salu_use(<2 x half> inreg %in, i32 inreg %val, ptr addrspace(1) %out) {207; GFX11-LABEL: s_fneg_v2f16_salu_use:208; GFX11: ; %bb.0:209; GFX11-NEXT: v_xor_b32_e64 v2, 0x80008000, s0210; GFX11-NEXT: s_cmp_eq_u32 s1, 0211; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)212; GFX11-NEXT: v_readfirstlane_b32 s0, v2213; GFX11-NEXT: s_cselect_b32 s0, s0, 0214; GFX11-NEXT: v_mov_b32_e32 v2, s0215; GFX11-NEXT: global_store_b32 v[0:1], v2, off216; GFX11-NEXT: s_endpgm217;218; GFX12-LABEL: s_fneg_v2f16_salu_use:219; GFX12: ; %bb.0:220; GFX12-NEXT: s_lshr_b32 s2, s0, 16221; GFX12-NEXT: s_xor_b32 s0, s0, 0x8000222; GFX12-NEXT: s_xor_b32 s2, s2, 0x8000223; GFX12-NEXT: s_cmp_eq_u32 s1, 0224; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2225; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)226; GFX12-NEXT: s_cselect_b32 s0, s0, 0227; GFX12-NEXT: v_mov_b32_e32 v2, s0228; GFX12-NEXT: global_store_b32 v[0:1], v2, off229; GFX12-NEXT: s_endpgm230 %fneg = fneg <2 x half> %in231 %cond = icmp eq i32 %val, 0232 %sel = select i1 %cond, <2 x half> %fneg, <2 x half> <half 0.0, half 0.0>233 store <2 x half> %sel, ptr addrspace(1) %out234 ret void235}236 237define amdgpu_ps void @v_fneg_v2f32(<2 x float> %in, ptr addrspace(1) %out) {238; GCN-LABEL: v_fneg_v2f32:239; GCN: ; %bb.0:240; GCN-NEXT: v_xor_b32_e32 v0, 0x80000000, v0241; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1242; GCN-NEXT: global_store_b64 v[2:3], v[0:1], off243; GCN-NEXT: s_endpgm244 %fneg = fneg <2 x float> %in245 store <2 x float> %fneg, ptr addrspace(1) %out246 ret void247}248define amdgpu_ps void @s_fneg_v2f32(<2 x float> inreg %in, ptr addrspace(1) %out) {249; GFX11-LABEL: s_fneg_v2f32:250; GFX11: ; %bb.0:251; GFX11-NEXT: v_xor_b32_e64 v2, 0x80000000, s0252; GFX11-NEXT: v_xor_b32_e64 v3, 0x80000000, s1253; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)254; GFX11-NEXT: v_readfirstlane_b32 s0, v2255; GFX11-NEXT: v_readfirstlane_b32 s1, v3256; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)257; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0258; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off259; GFX11-NEXT: s_endpgm260;261; GFX12-LABEL: s_fneg_v2f32:262; GFX12: ; %bb.0:263; GFX12-NEXT: s_xor_b32 s0, s0, 0x80000000264; GFX12-NEXT: s_xor_b32 s1, s1, 0x80000000265; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)266; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0267; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off268; GFX12-NEXT: s_endpgm269 %fneg = fneg <2 x float> %in270 store <2 x float> %fneg, ptr addrspace(1) %out271 ret void272}273define amdgpu_ps void @s_fneg_v2f32_salu_use(<2 x float> inreg %in, i32 inreg %val, ptr addrspace(1) %out) {274; GFX11-LABEL: s_fneg_v2f32_salu_use:275; GFX11: ; %bb.0:276; GFX11-NEXT: v_xor_b32_e64 v2, 0x80000000, s0277; GFX11-NEXT: v_xor_b32_e64 v3, 0x80000000, s1278; GFX11-NEXT: s_cmp_eq_u32 s2, 0279; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)280; GFX11-NEXT: v_readfirstlane_b32 s0, v2281; GFX11-NEXT: v_readfirstlane_b32 s1, v3282; GFX11-NEXT: s_cselect_b64 s[0:1], s[0:1], 0283; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)284; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0285; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off286; GFX11-NEXT: s_endpgm287;288; GFX12-LABEL: s_fneg_v2f32_salu_use:289; GFX12: ; %bb.0:290; GFX12-NEXT: s_xor_b32 s0, s0, 0x80000000291; GFX12-NEXT: s_xor_b32 s1, s1, 0x80000000292; GFX12-NEXT: s_cmp_eq_u32 s2, 0293; GFX12-NEXT: s_cselect_b64 s[0:1], s[0:1], 0294; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)295; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0296; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off297; GFX12-NEXT: s_endpgm298 %fneg = fneg <2 x float> %in299 %cond = icmp eq i32 %val, 0300 %sel = select i1 %cond, <2 x float> %fneg, <2 x float> <float 0.0, float 0.0>301 store <2 x float> %sel, ptr addrspace(1) %out302 ret void303}304