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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck %s3 4define amdgpu_ps void @uniform_fshr_i32(i32 inreg %lhs, i32 inreg %rhs, i32 inreg %amt, ptr %resptr) {5; CHECK-LABEL: uniform_fshr_i32:6; CHECK: ; %bb.0:7; CHECK-NEXT: v_mov_b32_e32 v2, s28; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)9; CHECK-NEXT: v_alignbit_b32 v2, s0, s1, v210; CHECK-NEXT: v_readfirstlane_b32 s0, v211; CHECK-NEXT: s_add_co_i32 s0, s0, s012; CHECK-NEXT: s_wait_alu depctr_sa_sdst(0)13; CHECK-NEXT: v_mov_b32_e32 v2, s014; CHECK-NEXT: flat_store_b32 v[0:1], v215; CHECK-NEXT: s_endpgm16 %vres = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)17 %add = add i32 %vres, %vres18 store i32 %add, ptr %resptr19 ret void20}21 22declare i32 @llvm.amdgcn.readfirstlane.i32(i32)23 24define amdgpu_ps void @divergent_fshr_i32(i32 %lhs, i32 %rhs, i32 %amt, ptr %resptr) {25; CHECK-LABEL: divergent_fshr_i32:26; CHECK: ; %bb.0:27; CHECK-NEXT: v_alignbit_b32 v0, v0, v1, v228; CHECK-NEXT: flat_store_b32 v[3:4], v029; CHECK-NEXT: s_endpgm30 %result = call i32 @llvm.fshr.i32(i32 %lhs, i32 %rhs, i32 %amt)31 store i32 %result, ptr %resptr32 ret void33}34 35declare i32 @llvm.fshr.i32(i32, i32, i32)36