60 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=WAVE64 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=WAVE32 %s4 5define amdgpu_ps void @i1_vcc_to_vcc_copy(i32 %val, float %a0, float %a1, float %b0, float %b1) {6; WAVE64-LABEL: i1_vcc_to_vcc_copy:7; WAVE64: ; %bb.0: ; %main_body8; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 2, v09; WAVE64-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc10; WAVE64-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc11; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm12; WAVE64-NEXT: s_endpgm13;14; WAVE32-LABEL: i1_vcc_to_vcc_copy:15; WAVE32: ; %bb.0: ; %main_body16; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v017; WAVE32-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo18; WAVE32-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo19; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm20; WAVE32-NEXT: s_endpgm21main_body:22 %vcc = icmp eq i32 %val, 223 %a = select i1 %vcc, float %a0, float %a124 %b = select i1 %vcc, float %b0, float %b125 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float poison, float poison, i1 true, i1 true)26 ret void27}28 29define amdgpu_ps void @i1_sgpr_to_vcc_copy(i32 inreg %val, float %a0, float %a1, float %b0, float %b1) {30; WAVE64-LABEL: i1_sgpr_to_vcc_copy:31; WAVE64: ; %bb.0: ; %main_body32; WAVE64-NEXT: s_cmp_eq_u32 s0, 233; WAVE64-NEXT: s_cselect_b32 s0, 1, 034; WAVE64-NEXT: s_and_b32 s0, 1, s035; WAVE64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s036; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc37; WAVE64-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc38; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm39; WAVE64-NEXT: s_endpgm40;41; WAVE32-LABEL: i1_sgpr_to_vcc_copy:42; WAVE32: ; %bb.0: ; %main_body43; WAVE32-NEXT: s_cmp_eq_u32 s0, 244; WAVE32-NEXT: s_cselect_b32 s0, 1, 045; WAVE32-NEXT: s_and_b32 s0, 1, s046; WAVE32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s047; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo48; WAVE32-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo49; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm50; WAVE32-NEXT: s_endpgm51main_body:52 %uniform_i1 = icmp eq i32 %val, 253 %a = select i1 %uniform_i1, float %a0, float %a154 %b = select i1 %uniform_i1, float %b0, float %b155 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %a, float %b, float poison, float poison, i1 true, i1 true)56 ret void57}58 59declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)60