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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -o - %s | FileCheck %s3 4define i32 @test_sgpr_reg_class_constraint() nounwind {5; CHECK-LABEL: test_sgpr_reg_class_constraint:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; CHECK-NEXT: ;;#ASMSTART9; CHECK-NEXT: s_mov_b32 s4, 710; CHECK-NEXT: ;;#ASMEND11; CHECK-NEXT: ;;#ASMSTART12; CHECK-NEXT: s_mov_b32 s5, 813; CHECK-NEXT: ;;#ASMEND14; CHECK-NEXT: ;;#ASMSTART15; CHECK-NEXT: s_add_u32 s4, s4, s516; CHECK-NEXT: ;;#ASMEND17; CHECK-NEXT: v_mov_b32_e32 v0, s418; CHECK-NEXT: s_setpc_b64 s[30:31]19entry:20 %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind21 %asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind22 %asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,s"(i32 %asm0, i32 %asm1) nounwind23 ret i32 %asm224}25 26define i32 @test_sgpr_matching_constraint() nounwind {27; CHECK-LABEL: test_sgpr_matching_constraint:28; CHECK: ; %bb.0: ; %entry29; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)30; CHECK-NEXT: ;;#ASMSTART31; CHECK-NEXT: s_mov_b32 s5, 732; CHECK-NEXT: ;;#ASMEND33; CHECK-NEXT: ;;#ASMSTART34; CHECK-NEXT: s_mov_b32 s4, 835; CHECK-NEXT: ;;#ASMEND36; CHECK-NEXT: ;;#ASMSTART37; CHECK-NEXT: s_add_u32 s4, s5, s438; CHECK-NEXT: ;;#ASMEND39; CHECK-NEXT: v_mov_b32_e32 v0, s440; CHECK-NEXT: s_setpc_b64 s[30:31]41entry:42 %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind43 %asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind44 %asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,0"(i32 %asm0, i32 %asm1) nounwind45 ret i32 %asm246}47 48define i32 @test_sgpr_to_vgpr_move_reg_class_constraint() nounwind {49; CHECK-LABEL: test_sgpr_to_vgpr_move_reg_class_constraint:50; CHECK: ; %bb.0: ; %entry51; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; CHECK-NEXT: ;;#ASMSTART53; CHECK-NEXT: s_mov_b32 s4, 754; CHECK-NEXT: ;;#ASMEND55; CHECK-NEXT: ;;#ASMSTART56; CHECK-NEXT: v_mov_b32 v0, s457; CHECK-NEXT: ;;#ASMEND58; CHECK-NEXT: s_setpc_b64 s[30:31]59entry:60 %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind61 %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,s"(i32 %asm0) nounwind62 ret i32 %asm163}64 65define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {66; CHECK-LABEL: test_sgpr_to_vgpr_move_matching_constraint:67; CHECK: ; %bb.0: ; %entry68; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)69; CHECK-NEXT: ;;#ASMSTART70; CHECK-NEXT: s_mov_b32 s4, 771; CHECK-NEXT: ;;#ASMEND72; CHECK-NEXT: v_mov_b32_e32 v0, s473; CHECK-NEXT: ;;#ASMSTART74; CHECK-NEXT: v_mov_b32 v0, v075; CHECK-NEXT: ;;#ASMEND76; CHECK-NEXT: s_setpc_b64 s[30:31]77entry:78 %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind79 %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind80 ret i32 %asm181}82 83!0 = !{i32 70}84