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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s6# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s7 8---9name: add_s3210legalized: true11regBankSelected: true12 13body: |14 bb.0:15 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr416 17 18 ; GFX6-LABEL: name: add_s3219 ; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr420 ; GFX6-NEXT: {{ $}}21 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr022 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr123 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr024 ; GFX6-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc25 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec26 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_ADD_I32_]], [[V_ADD_CO_U32_e64_]], 0, implicit $exec27 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_4:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_5:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[V_ADD_CO_U32_e64_2]], [[COPY2]], 0, implicit $exec28 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_CO_U32_e64_]], implicit [[V_ADD_CO_U32_e64_2]], implicit [[V_ADD_CO_U32_e64_4]]29 ;30 ; GFX9-LABEL: name: add_s3231 ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr432 ; GFX9-NEXT: {{ $}}33 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr034 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr135 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr036 ; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc37 ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec38 ; GFX9-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec39 ; GFX9-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec40 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]41 %0:sgpr(s32) = COPY $sgpr042 %1:sgpr(s32) = COPY $sgpr143 %2:vgpr(s32) = COPY $vgpr044 %3:vgpr(p1) = COPY $vgpr3_vgpr445 %4:sgpr(s32) = G_CONSTANT i32 146 %5:sgpr(s32) = G_CONSTANT i32 409647 48 %6:sgpr(s32) = G_ADD %0, %149 50 %7:vgpr(s32) = G_ADD %2, %651 52 %8:vgpr(s32) = G_ADD %6, %753 54 %9:vgpr(s32) = G_ADD %8, %255 56 S_ENDPGM 0, implicit %6, implicit %7, implicit %8, implicit %957 58...59 60---61name: add_neg_inline_const_64_to_sub_s32_s62legalized: true63regBankSelected: true64tracksRegLiveness: true65 66body: |67 bb.0:68 liveins: $sgpr069 70 ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s71 ; GFX6: liveins: $sgpr072 ; GFX6-NEXT: {{ $}}73 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr074 ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc75 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]]76 ;77 ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s78 ; GFX9: liveins: $sgpr079 ; GFX9-NEXT: {{ $}}80 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr081 ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def dead $scc82 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]]83 %0:sgpr(s32) = COPY $sgpr084 %1:sgpr(s32) = G_CONSTANT i32 -6485 %2:sgpr(s32) = G_ADD %0, %186 S_ENDPGM 0, implicit %287 88...89 90---91name: add_neg_inline_const_64_to_sub_s32_v92legalized: true93regBankSelected: true94tracksRegLiveness: true95 96body: |97 bb.0:98 liveins: $vgpr099 100 ; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v101 ; GFX6: liveins: $vgpr0102 ; GFX6-NEXT: {{ $}}103 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0104 ; GFX6-NEXT: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_SUB_CO_U32_e64 [[COPY]], 64, 0, implicit $exec105 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_]]106 ;107 ; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v108 ; GFX9: liveins: $vgpr0109 ; GFX9-NEXT: {{ $}}110 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0111 ; GFX9-NEXT: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec112 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]]113 %0:vgpr(s32) = COPY $vgpr0114 %1:vgpr(s32) = G_CONSTANT i32 -64115 %2:vgpr(s32) = G_ADD %0, %1116 S_ENDPGM 0, implicit %2117 118...119 120---121name: add_neg_inline_const_16_to_sub_s32_s122legalized: true123regBankSelected: true124tracksRegLiveness: true125 126body: |127 bb.0:128 liveins: $sgpr0129 130 ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s131 ; GFX6: liveins: $sgpr0132 ; GFX6-NEXT: {{ $}}133 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0134 ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16135 ; GFX6-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc136 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]137 ;138 ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s139 ; GFX9: liveins: $sgpr0140 ; GFX9-NEXT: {{ $}}141 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0142 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16143 ; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc144 ; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]145 %0:sgpr(s32) = COPY $sgpr0146 %1:sgpr(s32) = G_CONSTANT i32 16147 %2:sgpr(s32) = G_ADD %0, %1148 S_ENDPGM 0, implicit %2149 150...151 152---153name: add_neg_inline_const_16_to_sub_s32_v154legalized: true155regBankSelected: true156tracksRegLiveness: true157 158body: |159 bb.0:160 liveins: $vgpr0161 162 ; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v163 ; GFX6: liveins: $vgpr0164 ; GFX6-NEXT: {{ $}}165 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0166 ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec167 ; GFX6-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec168 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]169 ;170 ; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v171 ; GFX9: liveins: $vgpr0172 ; GFX9-NEXT: {{ $}}173 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0174 ; GFX9-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec175 ; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec176 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]177 %0:vgpr(s32) = COPY $vgpr0178 %1:vgpr(s32) = G_CONSTANT i32 16179 %2:vgpr(s32) = G_ADD %0, %1180 S_ENDPGM 0, implicit %2181 182...183