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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX11 %s6 7# Note: 16-bit instructions generally produce a 0 result in the high 16-bits on GFX8 and GFX9 and preserve high 16 bits on GFX10+8 9---10name: add_s1611legalized: true12regBankSelected: true13tracksRegLiveness: true14 15body: |16 bb.0:17 liveins: $vgpr0, $vgpr118 19 ; GFX6-LABEL: name: add_s1620 ; GFX6: liveins: $vgpr0, $vgpr121 ; GFX6-NEXT: {{ $}}22 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr023 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr124 ; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec25 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]26 ;27 ; GFX10-LABEL: name: add_s1628 ; GFX10: liveins: $vgpr0, $vgpr129 ; GFX10-NEXT: {{ $}}30 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr031 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr132 ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec33 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADD_NC_U16_e64_]]34 ;35 ; GFX11-LABEL: name: add_s1636 ; GFX11: liveins: $vgpr0, $vgpr137 ; GFX11-NEXT: {{ $}}38 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr039 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr140 ; GFX11-NEXT: [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec41 ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_ADD_NC_U16_fake16_e64_]]42 %0:vgpr(s32) = COPY $vgpr043 %1:vgpr(s32) = COPY $vgpr144 %2:vgpr(s16) = G_TRUNC %045 %3:vgpr(s16) = G_TRUNC %146 %4:vgpr(s16) = G_ADD %2, %347 S_ENDPGM 0, implicit %448 49...50 51---52name: add_s16_zext_to_s3253legalized: true54regBankSelected: true55tracksRegLiveness: true56 57body: |58 bb.0:59 liveins: $vgpr0, $vgpr160 61 ; GFX6-LABEL: name: add_s16_zext_to_s3262 ; GFX6: liveins: $vgpr0, $vgpr163 ; GFX6-NEXT: {{ $}}64 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr065 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr166 ; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec67 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]68 ;69 ; GFX10-LABEL: name: add_s16_zext_to_s3270 ; GFX10: liveins: $vgpr0, $vgpr171 ; GFX10-NEXT: {{ $}}72 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr073 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr174 ; GFX10-NEXT: [[V_ADD_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec75 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 6553576 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_ADD_NC_U16_e64_]], implicit $exec77 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]78 ;79 ; GFX11-LABEL: name: add_s16_zext_to_s3280 ; GFX11: liveins: $vgpr0, $vgpr181 ; GFX11-NEXT: {{ $}}82 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr083 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr184 ; GFX11-NEXT: [[V_ADD_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_NC_U16_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec85 ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 6553586 ; GFX11-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_ADD_NC_U16_fake16_e64_]], implicit $exec87 ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]88 %0:vgpr(s32) = COPY $vgpr089 %1:vgpr(s32) = COPY $vgpr190 %2:vgpr(s16) = G_TRUNC %091 %3:vgpr(s16) = G_TRUNC %192 %4:vgpr(s16) = G_ADD %2, %393 %5:vgpr(s32) = G_ZEXT %494 S_ENDPGM 0, implicit %595 96...97 98---99name: add_s16_neg_inline_const_64100legalized: true101regBankSelected: true102tracksRegLiveness: true103 104body: |105 bb.0:106 liveins: $vgpr0107 108 ; GFX6-LABEL: name: add_s16_neg_inline_const_64109 ; GFX6: liveins: $vgpr0110 ; GFX6-NEXT: {{ $}}111 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0112 ; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec113 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]114 ;115 ; GFX10-LABEL: name: add_s16_neg_inline_const_64116 ; GFX10: liveins: $vgpr0117 ; GFX10-NEXT: {{ $}}118 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0119 ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec120 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_SUB_NC_U16_e64_]]121 ;122 ; GFX11-LABEL: name: add_s16_neg_inline_const_64123 ; GFX11: liveins: $vgpr0124 ; GFX11-NEXT: {{ $}}125 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0126 ; GFX11-NEXT: [[V_SUB_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_fake16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec127 ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_SUB_NC_U16_fake16_e64_]]128 %0:vgpr(s32) = COPY $vgpr0129 %1:vgpr(s16) = G_TRUNC %0130 %2:vgpr(s16) = G_CONSTANT i16 -64131 %3:vgpr(s16) = G_ADD %1, %2132 S_ENDPGM 0, implicit %3133 134...135 136---137name: add_s16_neg_inline_const_64_zext_to_s32138legalized: true139regBankSelected: true140tracksRegLiveness: true141 142body: |143 bb.0:144 liveins: $vgpr0145 146 ; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32147 ; GFX6: liveins: $vgpr0148 ; GFX6-NEXT: {{ $}}149 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0150 ; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec151 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]152 ;153 ; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32154 ; GFX10: liveins: $vgpr0155 ; GFX10-NEXT: {{ $}}156 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0157 ; GFX10-NEXT: [[V_SUB_NC_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec158 ; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535159 ; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_SUB_NC_U16_e64_]], implicit $exec160 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]161 ;162 ; GFX11-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32163 ; GFX11: liveins: $vgpr0164 ; GFX11-NEXT: {{ $}}165 ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0166 ; GFX11-NEXT: [[V_SUB_NC_U16_fake16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_NC_U16_fake16_e64 0, [[COPY]], 0, 64, 0, 0, implicit $exec167 ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535168 ; GFX11-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[V_SUB_NC_U16_fake16_e64_]], implicit $exec169 ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]170 %0:vgpr(s32) = COPY $vgpr0171 %1:vgpr(s16) = G_TRUNC %0172 %2:vgpr(s16) = G_CONSTANT i16 -64173 %3:vgpr(s16) = G_ADD %1, %2174 %4:vgpr(s32) = G_ZEXT %3175 S_ENDPGM 0, implicit %4176 177...178