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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s4 5# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -filetype=null 2>&1 | FileCheck -check-prefix=SI-ERR %s6 7# SI-ERR-NOT: remark8# SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv)9# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs)10# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv)11# SI-ERR-NOT: remark12 13---14name: class_s16_vcc_sv15legalized: true16regBankSelected: true17tracksRegLiveness: true18 19body: |20 bb.0:21 liveins: $sgpr0, $vgpr022 ; WAVE32-LABEL: name: class_s16_vcc_sv23 ; WAVE32: liveins: $sgpr0, $vgpr024 ; WAVE32-NEXT: {{ $}}25 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr026 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr027 ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec28 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]29 ; WAVE64-LABEL: name: class_s16_vcc_sv30 ; WAVE64: liveins: $sgpr0, $vgpr031 ; WAVE64-NEXT: {{ $}}32 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr033 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr034 ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec35 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]36 %0:sgpr(s32) = COPY $sgpr037 %1:vgpr(s32) = COPY $vgpr038 %2:sgpr(s16) = G_TRUNC %039 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %140 S_ENDPGM 0, implicit %441...42 43---44name: class_s16_vcc_vs45legalized: true46regBankSelected: true47tracksRegLiveness: true48 49body: |50 bb.0:51 liveins: $sgpr0, $vgpr052 ; WAVE32-LABEL: name: class_s16_vcc_vs53 ; WAVE32: liveins: $sgpr0, $vgpr054 ; WAVE32-NEXT: {{ $}}55 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr056 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr057 ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec58 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]59 ; WAVE64-LABEL: name: class_s16_vcc_vs60 ; WAVE64: liveins: $sgpr0, $vgpr061 ; WAVE64-NEXT: {{ $}}62 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr063 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr064 ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec65 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]66 %0:vgpr(s32) = COPY $vgpr067 %1:sgpr(s32) = COPY $sgpr068 %2:vgpr(s16) = G_TRUNC %069 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %170 S_ENDPGM 0, implicit %471...72 73---74name: class_s16_vcc_vv75legalized: true76regBankSelected: true77tracksRegLiveness: true78 79body: |80 bb.0:81 liveins: $vgpr0, $vgpr182 ; WAVE32-LABEL: name: class_s16_vcc_vv83 ; WAVE32: liveins: $vgpr0, $vgpr184 ; WAVE32-NEXT: {{ $}}85 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr086 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr187 ; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec88 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]89 ; WAVE64-LABEL: name: class_s16_vcc_vv90 ; WAVE64: liveins: $vgpr0, $vgpr191 ; WAVE64-NEXT: {{ $}}92 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr093 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr194 ; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec95 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]96 %0:vgpr(s32) = COPY $vgpr097 %1:vgpr(s32) = COPY $vgpr198 %2:vgpr(s16) = G_TRUNC %099 %4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1100 S_ENDPGM 0, implicit %4101...102