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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s4 5---6name: cvt_pk_i16_vsv7legalized: true8regBankSelected: true9tracksRegLiveness: true10 11body: |12 bb.0:13 liveins: $sgpr0, $vgpr014 ; GCN-LABEL: name: cvt_pk_i16_vsv15 ; GCN: liveins: $sgpr0, $vgpr016 ; GCN-NEXT: {{ $}}17 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr018 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr019 ; GCN-NEXT: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec20 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]21 %0:sgpr(s32) = COPY $sgpr022 %1:vgpr(s32) = COPY $vgpr023 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %124 S_ENDPGM 0, implicit %225...26 27---28name: cvt_pk_i16_vvs29legalized: true30regBankSelected: true31tracksRegLiveness: true32 33body: |34 bb.0:35 liveins: $sgpr0, $vgpr036 37 ; GCN-LABEL: name: cvt_pk_i16_vvs38 ; GCN: liveins: $sgpr0, $vgpr039 ; GCN-NEXT: {{ $}}40 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr041 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr042 ; GCN-NEXT: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec43 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]44 %0:vgpr(s32) = COPY $vgpr045 %1:sgpr(s32) = COPY $sgpr046 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %147 S_ENDPGM 0, implicit %248...49 50---51name: cvt_pk_i16_vvv52legalized: true53regBankSelected: true54tracksRegLiveness: true55 56body: |57 bb.0:58 liveins: $vgpr0, $vgpr159 ; GCN-LABEL: name: cvt_pk_i16_vvv60 ; GCN: liveins: $vgpr0, $vgpr161 ; GCN-NEXT: {{ $}}62 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr063 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr164 ; GCN-NEXT: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec65 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]66 %0:vgpr(s32) = COPY $vgpr067 %1:vgpr(s32) = COPY $vgpr168 %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %169 S_ENDPGM 0, implicit %270...71