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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5 6name: ds_swizzle_07legalized: true8regBankSelected: true9tracksRegLiveness: true10 11 12body: |13 bb.0:14 liveins: $vgpr015 ; CHECK-LABEL: name: ds_swizzle_016 ; CHECK: liveins: $vgpr017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr019 ; CHECK-NEXT: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 0, 0, implicit $exec20 ; CHECK-NEXT: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]21 %0:vgpr(s32) = COPY $vgpr022 %1:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), %0, 023 S_ENDPGM 0, implicit %124 25...26 27---28 29name: ds_swizzle_6553530legalized: true31regBankSelected: true32tracksRegLiveness: true33 34 35body: |36 bb.0:37 liveins: $vgpr038 ; CHECK-LABEL: name: ds_swizzle_6553539 ; CHECK: liveins: $vgpr040 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr042 ; CHECK-NEXT: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 65535, 0, implicit $exec43 ; CHECK-NEXT: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]44 %0:vgpr(s32) = COPY $vgpr045 %1:vgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.ds.swizzle), %0, 6553546 S_ENDPGM 0, implicit %147 48...49