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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s3# RUN: llc -mtriple=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=ieee -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s6 7---8name: fmad_ftz_s32_vvvv9legalized: true10regBankSelected: true11tracksRegLiveness: true12 13body: |14 bb.0:15 liveins: $vgpr0, $vgpr1, $vgpr216 17 ; GCN-LABEL: name: fmad_ftz_s32_vvvv18 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr219 ; GCN-NEXT: {{ $}}20 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr021 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr122 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr223 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec24 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]25 %0:vgpr(s32) = COPY $vgpr026 %1:vgpr(s32) = COPY $vgpr127 %2:vgpr(s32) = COPY $vgpr228 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %229 S_ENDPGM 0, implicit %330...31 32---33name: fmad_ftz_s32_vsvv34legalized: true35regBankSelected: true36tracksRegLiveness: true37 38body: |39 bb.0:40 liveins: $sgpr0, $vgpr0, $vgpr141 42 ; GCN-LABEL: name: fmad_ftz_s32_vsvv43 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr144 ; GCN-NEXT: {{ $}}45 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr046 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr047 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr148 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec49 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]50 %0:sgpr(s32) = COPY $sgpr051 %1:vgpr(s32) = COPY $vgpr052 %2:vgpr(s32) = COPY $vgpr153 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %254 S_ENDPGM 0, implicit %355...56 57---58name: fmad_ftz_s32_vvsv59legalized: true60regBankSelected: true61tracksRegLiveness: true62 63body: |64 bb.0:65 liveins: $sgpr0, $vgpr0, $vgpr166 67 ; GCN-LABEL: name: fmad_ftz_s32_vvsv68 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr169 ; GCN-NEXT: {{ $}}70 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr071 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr072 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr173 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec74 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]75 %0:vgpr(s32) = COPY $vgpr076 %1:sgpr(s32) = COPY $sgpr077 %2:vgpr(s32) = COPY $vgpr178 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %279 S_ENDPGM 0, implicit %380...81 82---83name: fmad_ftz_s32_vvvs84legalized: true85regBankSelected: true86tracksRegLiveness: true87 88body: |89 bb.0:90 liveins: $sgpr0, $vgpr0, $vgpr191 92 ; GCN-LABEL: name: fmad_ftz_s32_vvvs93 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr194 ; GCN-NEXT: {{ $}}95 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr096 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr097 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr098 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]99 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec100 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]101 %0:vgpr(s32) = COPY $vgpr0102 %1:vgpr(s32) = COPY $vgpr0103 %2:sgpr(s32) = COPY $sgpr0104 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2105 S_ENDPGM 0, implicit %3106...107 108 109# Same SGPR used, so doesn't violate the constant bus restriction.110---111name: fmad_ftz_s32_vssv112legalized: true113regBankSelected: true114tracksRegLiveness: true115 116body: |117 bb.0:118 liveins: $sgpr0, $vgpr0119 120 ; GCN-LABEL: name: fmad_ftz_s32_vssv121 ; GCN: liveins: $sgpr0, $vgpr0122 ; GCN-NEXT: {{ $}}123 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0124 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0125 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec126 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]127 %0:sgpr(s32) = COPY $sgpr0128 %1:vgpr(s32) = COPY $vgpr0129 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %1130 S_ENDPGM 0, implicit %2131...132 133---134name: fmad_ftz_s32_vsvs135legalized: true136regBankSelected: true137tracksRegLiveness: true138 139body: |140 bb.0:141 liveins: $sgpr0, $vgpr0142 143 ; GCN-LABEL: name: fmad_ftz_s32_vsvs144 ; GCN: liveins: $sgpr0, $vgpr0145 ; GCN-NEXT: {{ $}}146 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0147 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0148 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]149 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec150 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]151 %0:sgpr(s32) = COPY $sgpr0152 %1:vgpr(s32) = COPY $vgpr0153 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %0154 S_ENDPGM 0, implicit %2155...156 157---158name: fmad_ftz_s32_vvss159legalized: true160regBankSelected: true161tracksRegLiveness: true162 163body: |164 bb.0:165 liveins: $sgpr0, $vgpr0166 167 ; GCN-LABEL: name: fmad_ftz_s32_vvss168 ; GCN: liveins: $sgpr0, $vgpr0169 ; GCN-NEXT: {{ $}}170 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0171 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0172 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]173 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec174 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]175 %0:sgpr(s32) = COPY $sgpr0176 %1:vgpr(s32) = COPY $vgpr0177 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %1, %0, %0178 S_ENDPGM 0, implicit %2179...180 181---182name: fmad_ftz_s32_vsss183legalized: true184regBankSelected: true185tracksRegLiveness: true186 187body: |188 bb.0:189 liveins: $sgpr0, $vgpr0190 191 ; GCN-LABEL: name: fmad_ftz_s32_vsss192 ; GCN: liveins: $sgpr0, $vgpr0193 ; GCN-NEXT: {{ $}}194 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0195 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]196 ; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec197 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]198 %0:sgpr(s32) = COPY $sgpr0199 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %0200 S_ENDPGM 0, implicit %1201...202 203 204# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.205# ---206# name: fmad_ftz_s32_vssv_constant_bus_violation207# legalized: true208# regBankSelected: true209# tracksRegLiveness: true210 211# body: |212# bb.0:213# liveins: $sgpr0, $sgpr1, $vgpr0214 215# %0:sgpr(s32) = COPY $sgpr0216# %1:sgpr(s32) = COPY $sgpr1217# %2:vgpr(s32) = COPY $vgpr0218# %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2219# S_ENDPGM 0, implicit %3220# ...221 222---223name: fmad_ftz_s32_vvv_fneg_v224legalized: true225regBankSelected: true226tracksRegLiveness: true227 228body: |229 bb.0:230 liveins: $vgpr0, $vgpr1, $vgpr2231 232 ; GCN-LABEL: name: fmad_ftz_s32_vvv_fneg_v233 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2234 ; GCN-NEXT: {{ $}}235 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0236 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1237 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2238 ; GCN-NEXT: [[V_MAD_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F32_e64 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec239 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAD_F32_e64_]]240 %0:vgpr(s32) = COPY $vgpr0241 %1:vgpr(s32) = COPY $vgpr1242 %2:vgpr(s32) = COPY $vgpr2243 %3:vgpr(s32) = G_FNEG %2244 %4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %3245 S_ENDPGM 0, implicit %4246...247