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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s3 4---5name: fmed3_s32_vvvv6legalized: true7regBankSelected: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $vgpr0, $vgpr1, $vgpr213 14 ; GCN-LABEL: name: fmed3_s32_vvvv15 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr216 ; GCN-NEXT: {{ $}}17 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr018 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr119 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr220 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec21 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]22 %0:vgpr(s32) = COPY $vgpr023 %1:vgpr(s32) = COPY $vgpr124 %2:vgpr(s32) = COPY $vgpr225 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %226 S_ENDPGM 0, implicit %327...28 29---30name: fmed3_s32_vsvv31legalized: true32regBankSelected: true33tracksRegLiveness: true34 35body: |36 bb.0:37 liveins: $sgpr0, $vgpr0, $vgpr138 39 ; GCN-LABEL: name: fmed3_s32_vsvv40 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr141 ; GCN-NEXT: {{ $}}42 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr043 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr044 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr145 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec46 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]47 %0:sgpr(s32) = COPY $sgpr048 %1:vgpr(s32) = COPY $vgpr049 %2:vgpr(s32) = COPY $vgpr150 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %251 S_ENDPGM 0, implicit %352...53 54---55name: fmed3_s32_vvsv56legalized: true57regBankSelected: true58tracksRegLiveness: true59 60body: |61 bb.0:62 liveins: $sgpr0, $vgpr0, $vgpr163 64 ; GCN-LABEL: name: fmed3_s32_vvsv65 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr166 ; GCN-NEXT: {{ $}}67 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr068 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr069 ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr170 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec71 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]72 %0:vgpr(s32) = COPY $vgpr073 %1:sgpr(s32) = COPY $sgpr074 %2:vgpr(s32) = COPY $vgpr175 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %276 S_ENDPGM 0, implicit %377...78 79---80name: fmed3_s32_vvvs81legalized: true82regBankSelected: true83tracksRegLiveness: true84 85body: |86 bb.0:87 liveins: $sgpr0, $vgpr0, $vgpr188 89 ; GCN-LABEL: name: fmed3_s32_vvvs90 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr191 ; GCN-NEXT: {{ $}}92 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr093 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr094 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr095 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec96 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]97 %0:vgpr(s32) = COPY $vgpr098 %1:vgpr(s32) = COPY $vgpr099 %2:sgpr(s32) = COPY $sgpr0100 %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2101 S_ENDPGM 0, implicit %3102...103 104 105# Same SGPR used, so doesn't violate the constant bus restriction.106---107name: fmed3_s32_vssv108legalized: true109regBankSelected: true110tracksRegLiveness: true111 112body: |113 bb.0:114 liveins: $sgpr0, $vgpr0115 116 ; GCN-LABEL: name: fmed3_s32_vssv117 ; GCN: liveins: $sgpr0, $vgpr0118 ; GCN-NEXT: {{ $}}119 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0120 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0121 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec122 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]123 %0:sgpr(s32) = COPY $sgpr0124 %1:vgpr(s32) = COPY $vgpr0125 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1126 S_ENDPGM 0, implicit %2127...128 129---130name: fmed3_s32_vsvs131legalized: true132regBankSelected: true133tracksRegLiveness: true134 135body: |136 bb.0:137 liveins: $sgpr0, $vgpr0138 139 ; GCN-LABEL: name: fmed3_s32_vsvs140 ; GCN: liveins: $sgpr0, $vgpr0141 ; GCN-NEXT: {{ $}}142 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0143 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0144 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec145 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]146 %0:sgpr(s32) = COPY $sgpr0147 %1:vgpr(s32) = COPY $vgpr0148 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0149 S_ENDPGM 0, implicit %2150...151 152---153name: fmed3_s32_vvss154legalized: true155regBankSelected: true156tracksRegLiveness: true157 158body: |159 bb.0:160 liveins: $sgpr0, $vgpr0161 162 ; GCN-LABEL: name: fmed3_s32_vvss163 ; GCN: liveins: $sgpr0, $vgpr0164 ; GCN-NEXT: {{ $}}165 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0166 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0167 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec168 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]169 %0:sgpr(s32) = COPY $sgpr0170 %1:vgpr(s32) = COPY $vgpr0171 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0172 S_ENDPGM 0, implicit %2173...174 175---176name: fmed3_s32_vsss177legalized: true178regBankSelected: true179tracksRegLiveness: true180 181body: |182 bb.0:183 liveins: $sgpr0, $vgpr0184 185 ; GCN-LABEL: name: fmed3_s32_vsss186 ; GCN: liveins: $sgpr0, $vgpr0187 ; GCN-NEXT: {{ $}}188 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0189 ; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec190 ; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]191 %0:sgpr(s32) = COPY $sgpr0192 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0193 S_ENDPGM 0, implicit %1194...195 196 197# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.198# ---199# name: fmed3_s32_vssv_constant_bus_violation200# legalized: true201# regBankSelected: true202# tracksRegLiveness: true203 204# body: |205# bb.0:206# liveins: $sgpr0, $sgpr1, $vgpr0207 208# %0:sgpr(s32) = COPY $sgpr0209# %1:sgpr(s32) = COPY $sgpr1210# %2:vgpr(s32) = COPY $vgpr0211# %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2212# S_ENDPGM 0, implicit %3213# ...214