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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: mulhi_i24_vsv6legalized: true7regBankSelected: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $sgpr0, $vgpr013 ; CHECK-LABEL: name: mulhi_i24_vsv14 ; CHECK: liveins: $sgpr0, $vgpr015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr017 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr018 ; CHECK-NEXT: [[V_MUL_HI_I32_I24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_I24_e64 [[COPY]], [[COPY1]], implicit $exec19 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_I24_e64_]]20 %0:sgpr(s32) = COPY $sgpr021 %1:vgpr(s32) = COPY $vgpr022 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.i24), %0, %123 S_ENDPGM 0, implicit %224...25 26---27name: mulhi_i24_vvs28legalized: true29regBankSelected: true30tracksRegLiveness: true31 32body: |33 bb.0:34 liveins: $sgpr0, $vgpr035 ; CHECK-LABEL: name: mulhi_i24_vvs36 ; CHECK: liveins: $sgpr0, $vgpr037 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr039 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr040 ; CHECK-NEXT: [[V_MUL_HI_I32_I24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_I24_e64 [[COPY]], [[COPY1]], implicit $exec41 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_I24_e64_]]42 %0:vgpr(s32) = COPY $vgpr043 %1:sgpr(s32) = COPY $sgpr044 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.i24), %0, %145 S_ENDPGM 0, implicit %246...47 48---49name: mulhi_i24_vvv50legalized: true51regBankSelected: true52tracksRegLiveness: true53 54body: |55 bb.0:56 liveins: $vgpr0, $vgpr157 ; CHECK-LABEL: name: mulhi_i24_vvv58 ; CHECK: liveins: $vgpr0, $vgpr159 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr061 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr162 ; CHECK-NEXT: [[V_MUL_HI_I32_I24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_HI_I32_I24_e64 [[COPY]], [[COPY1]], implicit $exec63 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_MUL_HI_I32_I24_e64_]]64 %0:vgpr(s32) = COPY $vgpr065 %1:vgpr(s32) = COPY $vgpr166 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mulhi.i24), %0, %167 S_ENDPGM 0, implicit %268...69