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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: rsq_s32_vs7legalized: true8regBankSelected: true9tracksRegLiveness: true10 11body: |12 bb.0:13 liveins: $sgpr014 15 ; CHECK-LABEL: name: rsq_s32_vs16 ; CHECK: liveins: $sgpr017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr019 ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec20 ; CHECK-NEXT: S_ENDPGM 0, implicit %121 %0:sgpr(s32) = COPY $sgpr022 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %023 S_ENDPGM 0, implicit %124...25 26---27name: rsq_s32_vv28legalized: true29regBankSelected: true30tracksRegLiveness: true31 32body: |33 bb.0:34 liveins: $vgpr035 36 ; CHECK-LABEL: name: rsq_s32_vv37 ; CHECK: liveins: $vgpr038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr040 ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec41 ; CHECK-NEXT: S_ENDPGM 0, implicit %142 %0:vgpr(s32) = COPY $vgpr043 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %044 S_ENDPGM 0, implicit %145...46 47---48name: rsq_s64_vs49legalized: true50regBankSelected: true51tracksRegLiveness: true52 53body: |54 bb.0:55 liveins: $sgpr0_sgpr156 57 ; CHECK-LABEL: name: rsq_s64_vs58 ; CHECK: liveins: $sgpr0_sgpr159 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr161 ; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec62 ; CHECK-NEXT: S_ENDPGM 0, implicit %163 %0:sgpr(s64) = COPY $sgpr0_sgpr164 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %065 S_ENDPGM 0, implicit %166...67 68---69name: rsq_s64_vv70legalized: true71regBankSelected: true72tracksRegLiveness: true73 74body: |75 bb.0:76 liveins: $vgpr0_vgpr177 78 ; CHECK-LABEL: name: rsq_s64_vv79 ; CHECK: liveins: $vgpr0_vgpr180 ; CHECK-NEXT: {{ $}}81 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr182 ; CHECK-NEXT: %1:vreg_64 = nofpexcept V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec83 ; CHECK-NEXT: S_ENDPGM 0, implicit %184 %0:vgpr(s64) = COPY $vgpr0_vgpr185 %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %086 S_ENDPGM 0, implicit %187...88