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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: sffbh_s32_ss6legalized: true7regBankSelected: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $sgpr013 14 ; CHECK-LABEL: name: sffbh_s32_ss15 ; CHECK: liveins: $sgpr016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr018 ; CHECK-NEXT: [[S_FLBIT_I32_:%[0-9]+]]:sreg_32 = S_FLBIT_I32 [[COPY]]19 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_]]20 %0:sgpr(s32) = COPY $sgpr021 %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %022 S_ENDPGM 0, implicit %123...24 25---26name: sffbh_s32_vs27legalized: true28regBankSelected: true29tracksRegLiveness: true30 31body: |32 bb.0:33 liveins: $sgpr034 35 ; CHECK-LABEL: name: sffbh_s32_vs36 ; CHECK: liveins: $sgpr037 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr039 ; CHECK-NEXT: [[V_FFBH_I32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_I32_e64 [[COPY]], implicit $exec40 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_I32_e64_]]41 %0:sgpr(s32) = COPY $sgpr042 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %043 S_ENDPGM 0, implicit %144...45 46---47name: sffbh_s32_vv48legalized: true49regBankSelected: true50tracksRegLiveness: true51 52body: |53 bb.0:54 liveins: $vgpr055 56 ; CHECK-LABEL: name: sffbh_s32_vv57 ; CHECK: liveins: $vgpr058 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr060 ; CHECK-NEXT: [[V_FFBH_I32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_I32_e64 [[COPY]], implicit $exec61 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_I32_e64_]]62 %0:vgpr(s32) = COPY $vgpr063 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sffbh), %064 S_ENDPGM 0, implicit %165...66