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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: sin_s32_vs7legalized: true8regBankSelected: true9tracksRegLiveness: true10 11body: |12 bb.0:13 liveins: $sgpr014 15 ; CHECK-LABEL: name: sin_s32_vs16 ; CHECK: liveins: $sgpr017 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr019 ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec20 ; CHECK-NEXT: S_ENDPGM 0, implicit %121 %0:sgpr(s32) = COPY $sgpr022 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %023 S_ENDPGM 0, implicit %124...25 26---27name: sin_s32_vv28legalized: true29regBankSelected: true30tracksRegLiveness: true31 32body: |33 bb.0:34 liveins: $vgpr035 36 ; CHECK-LABEL: name: sin_s32_vv37 ; CHECK: liveins: $vgpr038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr040 ; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec41 ; CHECK-NEXT: S_ENDPGM 0, implicit %142 %0:vgpr(s32) = COPY $vgpr043 %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %044 S_ENDPGM 0, implicit %145...46