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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -filetype=null 2>&1 | FileCheck -check-prefix=SI-ERR %s4 5# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:sgpr(s16) (in function: sin_s16_vs)6# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1:vgpr(s16) (in function: sin_s16_vv)7 8---9name: sin_s16_vs10legalized: true11regBankSelected: true12tracksRegLiveness: true13 14body: |15 bb.0:16 liveins: $sgpr017 18 ; CHECK-LABEL: name: sin_s16_vs19 ; CHECK: liveins: $sgpr020 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr022 ; CHECK-NEXT: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec23 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]24 %0:sgpr(s32) = COPY $sgpr025 %1:sgpr(s16) = G_TRUNC %026 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %127 S_ENDPGM 0, implicit %228...29 30---31name: sin_s16_vv32legalized: true33regBankSelected: true34tracksRegLiveness: true35 36body: |37 bb.0:38 liveins: $vgpr039 40 ; CHECK-LABEL: name: sin_s16_vv41 ; CHECK: liveins: $vgpr042 ; CHECK-NEXT: {{ $}}43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr044 ; CHECK-NEXT: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec45 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]46 %0:vgpr(s32) = COPY $vgpr047 %1:vgpr(s16) = G_TRUNC %048 %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %149 S_ENDPGM 0, implicit %250...51