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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1031 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1031 -mattr=+wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s4 5---6name: wave_address_s7legalized: true8regBankSelected: true9tracksRegLiveness: true10machineFunctionInfo:11 stackPtrOffsetReg: $sgpr3212body: |13 bb.0:14 ; WAVE32-LABEL: name: wave_address_s15 ; WAVE32: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 $sgpr32, 5, implicit-def dead $scc16 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]17 ;18 ; WAVE64-LABEL: name: wave_address_s19 ; WAVE64: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 $sgpr32, 6, implicit-def dead $scc20 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_LSHR_B32_]]21 %0:sgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr3222 S_ENDPGM 0, implicit %023...24 25---26name: wave_address_v27legalized: true28regBankSelected: true29tracksRegLiveness: true30machineFunctionInfo:31 stackPtrOffsetReg: $sgpr3232body: |33 bb.0:34 ; WAVE32-LABEL: name: wave_address_v35 ; WAVE32: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 5, $sgpr32, implicit $exec36 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]37 ;38 ; WAVE64-LABEL: name: wave_address_v39 ; WAVE64: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec40 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_LSHRREV_B32_e64_]]41 %0:vgpr(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr3242 S_ENDPGM 0, implicit %043...44