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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s4# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s5# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=WAVE32 %s6 7---8 9name: and_s1_vcc_vcc_vcc10legalized: true11regBankSelected: true12tracksRegLiveness: true13 14body: |15 bb.0:16 liveins: $vgpr0, $vgpr117 ; WAVE64-LABEL: name: and_s1_vcc_vcc_vcc18 ; WAVE64: liveins: $vgpr0, $vgpr119 ; WAVE64-NEXT: {{ $}}20 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr021 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr122 ; WAVE64-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec23 ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec24 ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec25 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc26 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]27 ;28 ; WAVE32-LABEL: name: and_s1_vcc_vcc_vcc29 ; WAVE32: liveins: $vgpr0, $vgpr130 ; WAVE32-NEXT: {{ $}}31 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr032 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr133 ; WAVE32-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec34 ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec35 ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec36 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc37 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]38 %0:vgpr(s32) = COPY $vgpr039 %1:vgpr(s32) = COPY $vgpr140 %2:vgpr(s32) = G_CONSTANT i32 041 %3:vcc(s1) = G_ICMP intpred(eq), %0, %242 %4:vcc(s1) = G_ICMP intpred(eq), %1, %243 %5:vcc(s1) = G_AND %3, %444 S_ENDPGM 0, implicit %545...46 47# Should fail to select48---49 50name: and_s1_sgpr_sgpr_sgpr51legalized: true52regBankSelected: true53tracksRegLiveness: true54 55body: |56 bb.0:57 liveins: $sgpr0, $sgpr158 ; WAVE64-LABEL: name: and_s1_sgpr_sgpr_sgpr59 ; WAVE64: liveins: $sgpr0, $sgpr160 ; WAVE64-NEXT: {{ $}}61 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr062 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr163 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc64 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]65 ;66 ; WAVE32-LABEL: name: and_s1_sgpr_sgpr_sgpr67 ; WAVE32: liveins: $sgpr0, $sgpr168 ; WAVE32-NEXT: {{ $}}69 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr070 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr171 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc72 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]73 %0:sgpr(s32) = COPY $sgpr074 %1:sgpr(s32) = COPY $sgpr175 %2:sgpr(s1) = G_TRUNC %076 %3:sgpr(s1) = G_TRUNC %177 %4:sgpr(s1) = G_AND %2, %378 S_ENDPGM 0, implicit %479...80 81---82 83name: and_s16_sgpr_sgpr_sgpr84legalized: true85regBankSelected: true86tracksRegLiveness: true87 88body: |89 bb.0:90 liveins: $sgpr0, $sgpr191 ; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr92 ; WAVE64: liveins: $sgpr0, $sgpr193 ; WAVE64-NEXT: {{ $}}94 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr095 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr196 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc97 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]98 ;99 ; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr100 ; WAVE32: liveins: $sgpr0, $sgpr1101 ; WAVE32-NEXT: {{ $}}102 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0103 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1104 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc105 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]106 %0:sgpr(s32) = COPY $sgpr0107 %1:sgpr(s32) = COPY $sgpr1108 %2:sgpr(s16) = G_TRUNC %0109 %3:sgpr(s16) = G_TRUNC %1110 %4:sgpr(s16) = G_AND %2, %3111 S_ENDPGM 0, implicit %4112...113 114---115 116name: and_s16_vgpr_vgpr_vgpr117legalized: true118regBankSelected: true119tracksRegLiveness: true120 121body: |122 bb.0:123 liveins: $vgpr0, $vgpr1124 ; WAVE64-LABEL: name: and_s16_vgpr_vgpr_vgpr125 ; WAVE64: liveins: $vgpr0, $vgpr1126 ; WAVE64-NEXT: {{ $}}127 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0128 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1129 ; WAVE64-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec130 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]131 ;132 ; WAVE32-LABEL: name: and_s16_vgpr_vgpr_vgpr133 ; WAVE32: liveins: $vgpr0, $vgpr1134 ; WAVE32-NEXT: {{ $}}135 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0136 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1137 ; WAVE32-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec138 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]139 %0:vgpr(s32) = COPY $vgpr0140 %1:vgpr(s32) = COPY $vgpr1141 %2:vgpr(s16) = G_TRUNC %0142 %3:vgpr(s16) = G_TRUNC %1143 %4:vgpr(s16) = G_AND %2, %3144 S_ENDPGM 0, implicit %4145...146 147---148 149name: and_s32_sgpr_sgpr_sgpr150legalized: true151regBankSelected: true152tracksRegLiveness: true153 154body: |155 bb.0:156 liveins: $sgpr0, $sgpr1157 ; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr158 ; WAVE64: liveins: $sgpr0, $sgpr1159 ; WAVE64-NEXT: {{ $}}160 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0161 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1162 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc163 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]164 ;165 ; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr166 ; WAVE32: liveins: $sgpr0, $sgpr1167 ; WAVE32-NEXT: {{ $}}168 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0169 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1170 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc171 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]172 %0:sgpr(s32) = COPY $sgpr0173 %1:sgpr(s32) = COPY $sgpr1174 %2:sgpr(s32) = G_AND %0, %1175 S_ENDPGM 0, implicit %2176...177 178---179 180name: and_s64_sgpr_sgpr_sgpr181legalized: true182regBankSelected: true183tracksRegLiveness: true184 185body: |186 bb.0:187 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3188 ; WAVE64-LABEL: name: and_s64_sgpr_sgpr_sgpr189 ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3190 ; WAVE64-NEXT: {{ $}}191 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1192 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3193 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc194 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]195 ;196 ; WAVE32-LABEL: name: and_s64_sgpr_sgpr_sgpr197 ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3198 ; WAVE32-NEXT: {{ $}}199 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1200 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3201 ; WAVE32-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc202 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]203 %0:sgpr(s64) = COPY $sgpr0_sgpr1204 %1:sgpr(s64) = COPY $sgpr2_sgpr3205 %2:sgpr(s64) = G_AND %0, %1206 S_ENDPGM 0, implicit %2207...208 209---210 211name: and_v2s16_sgpr_sgpr_sgpr212legalized: true213regBankSelected: true214tracksRegLiveness: true215 216body: |217 bb.0:218 liveins: $sgpr0, $sgpr1219 ; WAVE64-LABEL: name: and_v2s16_sgpr_sgpr_sgpr220 ; WAVE64: liveins: $sgpr0, $sgpr1221 ; WAVE64-NEXT: {{ $}}222 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0223 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1224 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc225 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]226 ;227 ; WAVE32-LABEL: name: and_v2s16_sgpr_sgpr_sgpr228 ; WAVE32: liveins: $sgpr0, $sgpr1229 ; WAVE32-NEXT: {{ $}}230 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0231 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1232 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc233 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]234 %0:sgpr(<2 x s16>) = COPY $sgpr0235 %1:sgpr(<2 x s16>) = COPY $sgpr1236 %2:sgpr(<2 x s16>) = G_AND %0, %1237 S_ENDPGM 0, implicit %2238...239 240---241 242name: and_v2s32_sgpr_sgpr_sgpr243legalized: true244regBankSelected: true245tracksRegLiveness: true246 247body: |248 bb.0:249 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3250 ; WAVE64-LABEL: name: and_v2s32_sgpr_sgpr_sgpr251 ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3252 ; WAVE64-NEXT: {{ $}}253 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1254 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3255 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc256 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]257 ;258 ; WAVE32-LABEL: name: and_v2s32_sgpr_sgpr_sgpr259 ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3260 ; WAVE32-NEXT: {{ $}}261 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1262 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3263 ; WAVE32-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc264 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]265 %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1266 %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3267 %2:sgpr(<2 x s32>) = G_AND %0, %1268 S_ENDPGM 0, implicit %2269...270 271---272 273name: and_v4s16_sgpr_sgpr_sgpr274legalized: true275regBankSelected: true276tracksRegLiveness: true277 278body: |279 bb.0:280 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3281 ; WAVE64-LABEL: name: and_v4s16_sgpr_sgpr_sgpr282 ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3283 ; WAVE64-NEXT: {{ $}}284 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1285 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3286 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc287 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]288 ;289 ; WAVE32-LABEL: name: and_v4s16_sgpr_sgpr_sgpr290 ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3291 ; WAVE32-NEXT: {{ $}}292 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1293 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3294 ; WAVE32-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[COPY1]], implicit-def dead $scc295 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]296 %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1297 %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3298 %2:sgpr(<4 x s16>) = G_AND %0, %1299 S_ENDPGM 0, implicit %2300...301 302---303 304name: and_s32_vgpr_vgpr_vgpr305legalized: true306regBankSelected: true307tracksRegLiveness: true308 309body: |310 bb.0:311 liveins: $vgpr0, $vgpr1312 ; WAVE64-LABEL: name: and_s32_vgpr_vgpr_vgpr313 ; WAVE64: liveins: $vgpr0, $vgpr1314 ; WAVE64-NEXT: {{ $}}315 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0316 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1317 ; WAVE64-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec318 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]319 ;320 ; WAVE32-LABEL: name: and_s32_vgpr_vgpr_vgpr321 ; WAVE32: liveins: $vgpr0, $vgpr1322 ; WAVE32-NEXT: {{ $}}323 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0324 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1325 ; WAVE32-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec326 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]327 %0:vgpr(s32) = COPY $vgpr0328 %1:vgpr(s32) = COPY $vgpr1329 %2:vgpr(s32) = G_AND %0, %1330 S_ENDPGM 0, implicit %2331...332 333---334 335name: and_v2s16_vgpr_vgpr_vgpr336legalized: true337regBankSelected: true338tracksRegLiveness: true339 340body: |341 bb.0:342 liveins: $vgpr0, $vgpr1343 ; WAVE64-LABEL: name: and_v2s16_vgpr_vgpr_vgpr344 ; WAVE64: liveins: $vgpr0, $vgpr1345 ; WAVE64-NEXT: {{ $}}346 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0347 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1348 ; WAVE64-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec349 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]350 ;351 ; WAVE32-LABEL: name: and_v2s16_vgpr_vgpr_vgpr352 ; WAVE32: liveins: $vgpr0, $vgpr1353 ; WAVE32-NEXT: {{ $}}354 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0355 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1356 ; WAVE32-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY]], [[COPY1]], implicit $exec357 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_AND_B32_e64_]]358 %0:vgpr(<2 x s16>) = COPY $vgpr0359 %1:vgpr(<2 x s16>) = COPY $vgpr1360 %2:vgpr(<2 x s16>) = G_AND %0, %1361 S_ENDPGM 0, implicit %2362...363 364 365# This should fail to select366---367 368name: and_s64_vgpr_vgpr_vgpr369legalized: true370regBankSelected: true371tracksRegLiveness: true372 373body: |374 bb.0:375 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3376 ; WAVE64-LABEL: name: and_s64_vgpr_vgpr_vgpr377 ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3378 ; WAVE64-NEXT: {{ $}}379 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1380 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3381 ; WAVE64-NEXT: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]382 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[AND]](s64)383 ;384 ; WAVE32-LABEL: name: and_s64_vgpr_vgpr_vgpr385 ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3386 ; WAVE32-NEXT: {{ $}}387 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1388 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3389 ; WAVE32-NEXT: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[COPY]], [[COPY1]]390 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[AND]](s64)391 %0:vgpr(s64) = COPY $vgpr0_vgpr1392 %1:vgpr(s64) = COPY $vgpr2_vgpr3393 %2:vgpr(s64) = G_AND %0, %1394 S_ENDPGM 0, implicit %2395...396 397---398 399name: and_s1_vcc_copy_to_vcc400legalized: true401regBankSelected: true402tracksRegLiveness: true403 404body: |405 bb.0:406 liveins: $vgpr0, $vgpr1407 ; WAVE64-LABEL: name: and_s1_vcc_copy_to_vcc408 ; WAVE64: liveins: $vgpr0, $vgpr1409 ; WAVE64-NEXT: {{ $}}410 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0411 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1412 ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec413 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec414 ; WAVE64-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec415 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec416 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc417 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]418 ;419 ; WAVE32-LABEL: name: and_s1_vcc_copy_to_vcc420 ; WAVE32: liveins: $vgpr0, $vgpr1421 ; WAVE32-NEXT: {{ $}}422 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0423 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1424 ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec425 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec426 ; WAVE32-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec427 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec428 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc429 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]430 %0:vgpr(s32) = COPY $vgpr0431 %1:vgpr(s32) = COPY $vgpr1432 %2:vgpr(s1) = G_TRUNC %0433 %3:vgpr(s1) = G_TRUNC %1434 %4:vcc(s1) = COPY %2435 %5:vcc(s1) = COPY %3436 %6:vcc(s1) = G_AND %4, %5437 S_ENDPGM 0, implicit %6438...439 440# The selector for the copy of the and result may constrain the result441# register of the and, losing that it is a VCCRegBank context.442 443# Works for wave32, should fail for wave64444---445name: copy_select_constrain_vcc_result_reg_wave32446legalized: true447regBankSelected: true448tracksRegLiveness: true449body: |450 bb.0:451 liveins: $vgpr0, $sgpr0452 453 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32454 ; WAVE64: liveins: $vgpr0, $sgpr0455 ; WAVE64-NEXT: {{ $}}456 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0457 ; WAVE64-NEXT: %sgpr0:sreg_32 = COPY $sgpr0458 ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec459 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec460 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc461 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec462 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc463 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B64_]]464 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]]465 ;466 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32467 ; WAVE32: liveins: $vgpr0, $sgpr0468 ; WAVE32-NEXT: {{ $}}469 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0470 ; WAVE32-NEXT: %sgpr0:sreg_32 = COPY $sgpr0471 ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec472 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec473 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc474 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec475 ; WAVE32-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc476 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_AND_B32_1]]477 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]478 %1:vgpr(s32) = COPY $vgpr0479 %0:vgpr(s1) = G_TRUNC %1(s32)480 %sgpr0:sgpr(s32) = COPY $sgpr0481 %2:sgpr(s1) = G_TRUNC %sgpr0482 %6:sgpr(s32) = G_CONSTANT i32 0483 %7:sgpr(p1) = G_IMPLICIT_DEF484 %9:vcc(s1) = COPY %0(s1)485 %10:vcc(s1) = COPY %2(s1)486 %8:vcc(s1) = G_AND %9, %10487 %3:sreg_32_xm0(s1) = COPY %8(s1)488 S_ENDPGM 0, implicit %3489 490...491 492# Works for wave64, should fail for wave32493---494name: copy_select_constrain_vcc_result_reg_wave64495legalized: true496regBankSelected: true497tracksRegLiveness: true498body: |499 bb.0:500 liveins: $vgpr0, $sgpr0501 502 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64503 ; WAVE64: liveins: $vgpr0, $sgpr0504 ; WAVE64-NEXT: {{ $}}505 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0506 ; WAVE64-NEXT: %sgpr0:sreg_32 = COPY $sgpr0507 ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec508 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec509 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc510 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec511 ; WAVE64-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc512 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B64_]]513 ;514 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64515 ; WAVE32: liveins: $vgpr0, $sgpr0516 ; WAVE32-NEXT: {{ $}}517 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0518 ; WAVE32-NEXT: %sgpr0:sreg_32 = COPY $sgpr0519 ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec520 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec521 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc522 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec523 ; WAVE32-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc524 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_AND_B32_1]]525 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]526 %1:vgpr(s32) = COPY $vgpr0527 %0:vgpr(s1) = G_TRUNC %1(s32)528 %sgpr0:sgpr(s32) = COPY $sgpr0529 %2:sgpr(s1) = G_TRUNC %sgpr0530 %6:sgpr(s32) = G_CONSTANT i32 0531 %7:sgpr(p1) = G_IMPLICIT_DEF532 %9:vcc(s1) = COPY %0(s1)533 %10:vcc(s1) = COPY %2(s1)534 %8:vcc(s1) = G_AND %9, %10535 %3:sreg_64_xexec(s1) = COPY %8(s1)536 S_ENDPGM 0, implicit %3537 538...539 540---541 542name: and_s32_sgpr_sgpr_sgpr_result_reg_class543legalized: true544regBankSelected: true545tracksRegLiveness: true546 547body: |548 bb.0:549 liveins: $sgpr0, $sgpr1550 ; WAVE64-LABEL: name: and_s32_sgpr_sgpr_sgpr_result_reg_class551 ; WAVE64: liveins: $sgpr0, $sgpr1552 ; WAVE64-NEXT: {{ $}}553 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0554 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1555 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc556 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]557 ;558 ; WAVE32-LABEL: name: and_s32_sgpr_sgpr_sgpr_result_reg_class559 ; WAVE32: liveins: $sgpr0, $sgpr1560 ; WAVE32-NEXT: {{ $}}561 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0562 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1563 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], [[COPY1]], implicit-def dead $scc564 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_AND_B32_]]565 %0:sgpr(s32) = COPY $sgpr0566 %1:sgpr(s32) = COPY $sgpr1567 %2:sreg_32(s32) = G_AND %0, %1568 S_ENDPGM 0, implicit %2569...570