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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s3 4---5name: bitreverse_i32_ss6legalized: true7regBankSelected: true8 9body: |10 bb.0:11 liveins: $sgpr012 ; CHECK-LABEL: name: bitreverse_i32_ss13 ; CHECK: liveins: $sgpr014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr016 ; CHECK-NEXT: [[S_BREV_B32_:%[0-9]+]]:sreg_32 = S_BREV_B32 [[COPY]]17 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_BREV_B32_]]18 %0:sgpr(s32) = COPY $sgpr019 %1:sgpr(s32) = G_BITREVERSE %020 S_ENDPGM 0, implicit %121...22 23---24name: bitreverse_i32_vv25legalized: true26regBankSelected: true27 28body: |29 bb.0:30 liveins: $vgpr031 ; CHECK-LABEL: name: bitreverse_i32_vv32 ; CHECK: liveins: $vgpr033 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr035 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec36 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]37 %0:vgpr(s32) = COPY $vgpr038 %1:vgpr(s32) = G_BITREVERSE %039 S_ENDPGM 0, implicit %140...41 42---43name: bitreverse_i32_vs44legalized: true45regBankSelected: true46 47body: |48 bb.0:49 liveins: $sgpr050 ; CHECK-LABEL: name: bitreverse_i32_vs51 ; CHECK: liveins: $sgpr052 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr054 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY]], implicit $exec55 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFREV_B32_e64_]]56 %0:sgpr(s32) = COPY $sgpr057 %1:vgpr(s32) = G_BITREVERSE %058 S_ENDPGM 0, implicit %159...60 61---62name: bitreverse_i64_ss63legalized: true64regBankSelected: true65 66body: |67 bb.0:68 liveins: $sgpr0_sgpr169 ; CHECK-LABEL: name: bitreverse_i64_ss70 ; CHECK: liveins: $sgpr0_sgpr171 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr173 ; CHECK-NEXT: [[S_BREV_B64_:%[0-9]+]]:sreg_64 = S_BREV_B64 [[COPY]]74 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_BREV_B64_]]75 %0:sgpr(s64) = COPY $sgpr0_sgpr176 %1:sgpr(s64) = G_BITREVERSE %077 S_ENDPGM 0, implicit %178...79 80---81name: bitreverse_i64_vv82legalized: true83regBankSelected: true84 85body: |86 bb.0:87 liveins: $vgpr0_vgpr188 ; CHECK-LABEL: name: bitreverse_i64_vv89 ; CHECK: liveins: $vgpr0_vgpr190 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr192 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub093 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub194 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec95 ; CHECK-NEXT: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec96 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub197 ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]98 %0:vgpr(s64) = COPY $vgpr0_vgpr199 %2:vgpr(s32), %3:vgpr(s32) = G_UNMERGE_VALUES %0(s64)100 %4:vgpr(s32) = G_BITREVERSE %3101 %5:vgpr(s32) = G_BITREVERSE %2102 %1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32)103 S_ENDPGM 0, implicit %1104...105 106---107name: bitreverse_i64_vs108legalized: true109regBankSelected: true110 111body: |112 bb.0:113 liveins: $sgpr0_sgpr1114 ; CHECK-LABEL: name: bitreverse_i64_vs115 ; CHECK: liveins: $sgpr0_sgpr1116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0119 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1120 ; CHECK-NEXT: [[V_BFREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY2]], implicit $exec121 ; CHECK-NEXT: [[V_BFREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_BFREV_B32_e64 [[COPY1]], implicit $exec122 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_BFREV_B32_e64_]], %subreg.sub0, [[V_BFREV_B32_e64_1]], %subreg.sub1123 ; CHECK-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]124 %0:sgpr(s64) = COPY $sgpr0_sgpr1125 %2:sgpr(s32), %3:sgpr(s32) = G_UNMERGE_VALUES %0(s64)126 %4:vgpr(s32) = G_BITREVERSE %3127 %5:vgpr(s32) = G_BITREVERSE %2128 %1:vgpr(s64) = G_MERGE_VALUES %4(s32), %5(s32)129 S_ENDPGM 0, implicit %1130...131