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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s3 4---5name: test_build_vector_v_v2s32_v_s32_v_s326legalized: true7regBankSelected: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $vgpr0, $vgpr113 14 ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_v_s3215 ; GCN: liveins: $vgpr0, $vgpr116 ; GCN-NEXT: {{ $}}17 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr018 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr119 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub120 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]21 %0:vgpr(s32) = COPY $vgpr022 %1:vgpr(s32) = COPY $vgpr123 %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %124 S_ENDPGM 0, implicit %225...26 27---28name: test_build_vector_v_v2s32_s_s32_v_s3229legalized: true30regBankSelected: true31tracksRegLiveness: true32 33body: |34 bb.0:35 liveins: $sgpr0, $vgpr036 37 ; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s3238 ; GCN: liveins: $sgpr0, $vgpr039 ; GCN-NEXT: {{ $}}40 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr041 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr042 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub143 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]44 %0:sgpr(s32) = COPY $sgpr045 %1:vgpr(s32) = COPY $vgpr046 %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %147 S_ENDPGM 0, implicit %248...49 50---51name: test_build_vector_v_v2s32_v_s32_s_s3252legalized: true53regBankSelected: true54tracksRegLiveness: true55 56body: |57 bb.0:58 liveins: $sgpr0, $vgpr059 60 ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s3261 ; GCN: liveins: $sgpr0, $vgpr062 ; GCN-NEXT: {{ $}}63 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr064 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr065 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub166 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]67 %0:vgpr(s32) = COPY $vgpr068 %1:sgpr(s32) = COPY $sgpr069 %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %170 S_ENDPGM 0, implicit %271...72 73---74name: test_build_vector_s_v2s32_s_s32_s_s3275legalized: true76regBankSelected: true77tracksRegLiveness: true78 79body: |80 bb.0:81 liveins: $sgpr0, $sgpr182 83 ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s3284 ; GCN: liveins: $sgpr0, $sgpr185 ; GCN-NEXT: {{ $}}86 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr087 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr188 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub189 ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]90 %0:sgpr(s32) = COPY $sgpr091 %1:sgpr(s32) = COPY $sgpr192 %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %193 S_ENDPGM 0, implicit %294...95 96---97name: test_build_vector_s_v2s64_s_s64_s_s6498legalized: true99regBankSelected: true100tracksRegLiveness: true101 102body: |103 bb.0:104 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3105 106 ; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64107 ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3108 ; GCN-NEXT: {{ $}}109 ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1110 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3111 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3112 ; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]113 %0:sgpr(s64) = COPY $sgpr0_sgpr1114 %1:sgpr(s64) = COPY $sgpr2_sgpr3115 %4:sgpr(<2 x s64>) = G_BUILD_VECTOR %0, %1116 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4117...118