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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx700 -run-pass=instruction-select %s -o - | FileCheck -check-prefixes=GFX7 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx803 -run-pass=instruction-select %s -o - | FileCheck -check-prefixes=GF8 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select %s -o - | FileCheck -check-prefixes=GFX11 %s5 6---7name: test_copy_scc_vcc8legalized: true9regBankSelected: true10tracksRegLiveness: true11body: |12 bb.0:13 ; GFX7-LABEL: name: test_copy_scc_vcc14 ; GFX7: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF15 ; GFX7-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[DEF]], [[DEF]], implicit-def $scc16 ; GFX7-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc17 ; GFX7-NEXT: $sgpr0 = COPY [[COPY]]18 ; GFX7-NEXT: S_ENDPGM 0, implicit $sgpr019 ;20 ; GF8-LABEL: name: test_copy_scc_vcc21 ; GF8: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF22 ; GF8-NEXT: S_CMP_LG_U64 [[DEF]], 0, implicit-def $scc23 ; GF8-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc24 ; GF8-NEXT: $sgpr0 = COPY [[COPY]]25 ; GF8-NEXT: S_ENDPGM 0, implicit $sgpr026 ;27 ; GFX11-LABEL: name: test_copy_scc_vcc28 ; GFX11: [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF29 ; GFX11-NEXT: S_CMP_LG_U32 [[DEF]], 0, implicit-def $scc30 ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $scc31 ; GFX11-NEXT: $sgpr0 = COPY [[COPY]]32 ; GFX11-NEXT: S_ENDPGM 0, implicit $sgpr033 %0:vcc(s1) = G_IMPLICIT_DEF34 %1:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC %035 $sgpr0 = COPY %136 S_ENDPGM 0, implicit $sgpr037...38