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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: ctlz_zero_undef_s32_ss6legalized: true7regBankSelected: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $sgpr013 14 ; CHECK-LABEL: name: ctlz_zero_undef_s32_ss15 ; CHECK: liveins: $sgpr016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr018 ; CHECK-NEXT: [[S_FLBIT_I32_B32_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B32 [[COPY]]19 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_B32_]]20 %0:sgpr(s32) = COPY $sgpr021 %1:sgpr(s32) = G_CTLZ_ZERO_UNDEF %022 S_ENDPGM 0, implicit %123...24 25---26name: ctlz_zero_undef_s32_vs27legalized: true28regBankSelected: true29tracksRegLiveness: true30 31body: |32 bb.0:33 liveins: $sgpr034 35 ; CHECK-LABEL: name: ctlz_zero_undef_s32_vs36 ; CHECK: liveins: $sgpr037 ; CHECK-NEXT: {{ $}}38 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr039 ; CHECK-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec40 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]41 %0:sgpr(s32) = COPY $sgpr042 %1:vgpr(s32) = G_CTLZ_ZERO_UNDEF %043 S_ENDPGM 0, implicit %144...45 46---47name: ctlz_zero_undef_s32_vv48legalized: true49regBankSelected: true50tracksRegLiveness: true51 52body: |53 bb.0:54 liveins: $vgpr055 56 ; CHECK-LABEL: name: ctlz_zero_undef_s32_vv57 ; CHECK: liveins: $vgpr058 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr060 ; CHECK-NEXT: [[V_FFBH_U32_e64_:%[0-9]+]]:vgpr_32 = V_FFBH_U32_e64 [[COPY]], implicit $exec61 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_FFBH_U32_e64_]]62 %0:vgpr(s32) = COPY $vgpr063 %1:vgpr(s32) = G_CTLZ_ZERO_UNDEF %064 S_ENDPGM 0, implicit %165...66 67---68name: ctlz_zero_undef_s64_ss69legalized: true70regBankSelected: true71tracksRegLiveness: true72 73body: |74 bb.0:75 liveins: $sgpr0_sgpr176 77 ; CHECK-LABEL: name: ctlz_zero_undef_s64_ss78 ; CHECK: liveins: $sgpr0_sgpr179 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr181 ; CHECK-NEXT: [[S_FLBIT_I32_B64_:%[0-9]+]]:sreg_32 = S_FLBIT_I32_B64 [[COPY]]82 ; CHECK-NEXT: S_ENDPGM 0, implicit [[S_FLBIT_I32_B64_]]83 %0:sgpr(s64) = COPY $sgpr0_sgpr184 %1:sgpr(s32) = G_CTLZ_ZERO_UNDEF %085 S_ENDPGM 0, implicit %186...87