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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: fexp2_s16_vs6legalized: true7regBankSelected: true8tracksRegLiveness: true9 10body: |11 bb.0:12 liveins: $sgpr013 14 ; CHECK-LABEL: name: fexp2_s16_vs15 ; CHECK: liveins: $sgpr016 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr018 ; CHECK-NEXT: [[V_EXP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec19 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_EXP_F16_e64_]]20 %0:sgpr(s32) = COPY $sgpr021 %1:sgpr(s16) = G_TRUNC %022 %2:vgpr(s16) = G_FEXP2 %123 S_ENDPGM 0, implicit %224...25 26---27name: fexp2_s16_vv28legalized: true29regBankSelected: true30tracksRegLiveness: true31 32body: |33 bb.0:34 liveins: $vgpr035 36 ; CHECK-LABEL: name: fexp2_s16_vv37 ; CHECK: liveins: $vgpr038 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr040 ; CHECK-NEXT: [[V_EXP_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec41 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_EXP_F16_e64_]]42 %0:vgpr(s32) = COPY $vgpr043 %1:vgpr(s16) = G_TRUNC %044 %2:vgpr(s16) = G_FEXP2 %145 S_ENDPGM 0, implicit %246...47