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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GFX9 %s5 6---7name: fmul_v2f16_vv8legalized: true9regBankSelected: true10 11body: |12 bb.0:13 liveins: $vgpr0, $vgpr114 15 ; GFX9-LABEL: name: fmul_v2f16_vv16 ; GFX9: liveins: $vgpr0, $vgpr117 ; GFX9-NEXT: {{ $}}18 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr019 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr120 ; GFX9-NEXT: %2:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec21 ; GFX9-NEXT: S_ENDPGM 0, implicit %222 %0:vgpr(<2 x s16>) = COPY $vgpr023 %1:vgpr(<2 x s16>) = COPY $vgpr124 %2:vgpr(<2 x s16>) = G_FMUL %0, %125 S_ENDPGM 0, implicit %226...27 28---29name: fmul_v2f16_fneg_v_fneg_v30legalized: true31regBankSelected: true32 33body: |34 bb.0:35 liveins: $vgpr0, $vgpr136 37 ; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v38 ; GFX9: liveins: $vgpr0, $vgpr139 ; GFX9-NEXT: {{ $}}40 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr041 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr142 ; GFX9-NEXT: %4:vgpr_32 = nofpexcept V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec43 ; GFX9-NEXT: S_ENDPGM 0, implicit %444 %0:vgpr(<2 x s16>) = COPY $vgpr045 %1:vgpr(<2 x s16>) = COPY $vgpr146 %2:vgpr(<2 x s16>) = G_FNEG %047 %3:vgpr(<2 x s16>) = G_FNEG %148 %4:vgpr(<2 x s16>) = G_FMUL %2, %349 S_ENDPGM 0, implicit %450...51 52---53name: fmul_v2f16_fneg_lo_v_v54legalized: true55regBankSelected: true56 57body: |58 bb.0:59 liveins: $vgpr0, $vgpr1, $vgpr260 61 ; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v62 ; GFX9: liveins: $vgpr0, $vgpr1, $vgpr263 ; GFX9-NEXT: {{ $}}64 ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr065 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr166 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr267 ; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 3276868 ; GFX9-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec69 ; GFX9-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[V_XOR_B32_e64_]], implicit $exec70 ; GFX9-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, [[V_AND_B32_e32_]], implicit $exec71 ; GFX9-NEXT: %7:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[V_LSHL_OR_B32_e64_]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec72 ; GFX9-NEXT: S_ENDPGM 0, implicit %773 %0:vgpr(<2 x s16>) = COPY $vgpr074 %1:vgpr(s32) = COPY $vgpr175 %2:vgpr(s32) = COPY $vgpr276 %3:vgpr(s16) = G_TRUNC %177 %4:vgpr(s16) = G_FNEG %378 %5:vgpr(s32) = G_ANYEXT %479 %6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %280 %7:vgpr(<2 x s16>) = G_FMUL %6, %081 S_ENDPGM 0, implicit %782...83