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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN %s3 4---5 6name: implicit_def_s32_sgpr7legalized: true8regBankSelected: true9 10body: |11 bb.0:12 ; GCN-LABEL: name: implicit_def_s32_sgpr13 ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF14 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]15 %0:sgpr(s32) = G_IMPLICIT_DEF16 S_ENDPGM 0, implicit %017...18---19 20name: implicit_def_s32_vgpr21legalized: true22regBankSelected: true23 24body: |25 bb.0:26 ; GCN-LABEL: name: implicit_def_s32_vgpr27 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF28 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]29 %0:vgpr(s32) = G_IMPLICIT_DEF30 S_ENDPGM 0, implicit %031...32 33---34 35name: implicit_def_s64_sgpr36legalized: true37regBankSelected: true38 39body: |40 bb.0:41 ; GCN-LABEL: name: implicit_def_s64_sgpr42 ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF43 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]44 %0:sgpr(s64) = G_IMPLICIT_DEF45 S_ENDPGM 0, implicit %046...47 48---49 50name: implicit_def_s64_vgpr51legalized: true52regBankSelected: true53 54body: |55 bb.0:56 ; GCN-LABEL: name: implicit_def_s64_vgpr57 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF58 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]59 %0:vgpr(s64) = G_IMPLICIT_DEF60 S_ENDPGM 0, implicit %061...62 63---64name: implicit_def_p0_sgpr65legalized: true66regBankSelected: true67 68body: |69 bb.0:70 ; GCN-LABEL: name: implicit_def_p0_sgpr71 ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF72 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]73 %0:sgpr(p0) = G_IMPLICIT_DEF74 S_ENDPGM 0, implicit %075...76 77---78name: implicit_def_p0_vgpr79legalized: true80regBankSelected: true81 82body: |83 bb.0:84 ; GCN-LABEL: name: implicit_def_p0_vgpr85 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF86 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]87 %0:vgpr(p0) = G_IMPLICIT_DEF88 S_ENDPGM 0, implicit %089...90 91---92 93name: implicit_def_p1_vgpr94legalized: true95regBankSelected: true96 97body: |98 bb.0:99 ; GCN-LABEL: name: implicit_def_p1_vgpr100 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF101 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec102 ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)103 %0:vgpr(p1) = G_IMPLICIT_DEF104 %1:vgpr(s32) = G_CONSTANT i32 4105 G_STORE %1, %0 :: (store (s32), addrspace 1)106...107 108---109 110name: implicit_def_p3_vgpr111legalized: true112regBankSelected: true113 114body: |115 bb.0:116 ; GCN-LABEL: name: implicit_def_p3_vgpr117 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF118 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec119 ; GCN-NEXT: $m0 = S_MOV_B32 -1120 ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)121 %0:vgpr(p3) = G_IMPLICIT_DEF122 %1:vgpr(s32) = G_CONSTANT i32 4123 G_STORE %1, %0 :: (store (s32), addrspace 1)124...125 126---127 128name: implicit_def_p4_vgpr129legalized: true130regBankSelected: true131 132body: |133 bb.0:134 ; GCN-LABEL: name: implicit_def_p4_vgpr135 ; GCN: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF136 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec137 ; GCN-NEXT: FLAT_STORE_DWORD [[DEF]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32), addrspace 1)138 %0:vgpr(p4) = G_IMPLICIT_DEF139 %1:vgpr(s32) = G_CONSTANT i32 4140 G_STORE %1, %0 :: (store (s32), addrspace 1)141...142 143---144 145name: implicit_def_s1_vgpr146legalized: true147regBankSelected: true148 149body: |150 bb.0:151 ; GCN-LABEL: name: implicit_def_s1_vgpr152 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF153 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]154 %0:vgpr(s1) = G_IMPLICIT_DEF155 S_ENDPGM 0, implicit %0156...157 158---159 160name: implicit_def_s1_sgpr161legalized: true162regBankSelected: true163 164body: |165 bb.0:166 ; GCN-LABEL: name: implicit_def_s1_sgpr167 ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF168 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]169 %0:sgpr(s1) = G_IMPLICIT_DEF170 S_ENDPGM 0, implicit %0171...172 173---174 175name: implicit_def_s1_vcc176legalized: true177regBankSelected: true178 179body: |180 bb.0:181 ; GCN-LABEL: name: implicit_def_s1_vcc182 ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF183 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]184 %0:vcc(s1) = G_IMPLICIT_DEF185 S_ENDPGM 0, implicit %0186...187 188---189 190name: implicit_def_s1024_sgpr191legalized: true192regBankSelected: true193 194body: |195 bb.0:196 ; GCN-LABEL: name: implicit_def_s1024_sgpr197 ; GCN: [[DEF:%[0-9]+]]:sgpr_1024 = IMPLICIT_DEF198 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]199 %0:sgpr(s1024) = G_IMPLICIT_DEF200 S_ENDPGM 0, implicit %0201...202---203 204name: implicit_def_s1024_vgpr205legalized: true206regBankSelected: true207 208body: |209 bb.0:210 ; GCN-LABEL: name: implicit_def_s1024_vgpr211 ; GCN: [[DEF:%[0-9]+]]:vreg_1024 = IMPLICIT_DEF212 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]213 %0:vgpr(s1024) = G_IMPLICIT_DEF214 S_ENDPGM 0, implicit %0215...216