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1# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI2# RUN: llc -mtriple=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,GFX95 6--- |7 define amdgpu_kernel void @smrd_imm(ptr addrspace(4) %const0) { ret void }8 define amdgpu_kernel void @smrd_wide() { ret void }9 define amdgpu_kernel void @constant_address_positive() { ret void }10 define amdgpu_kernel void @smrd_sgpr() { ret void }11 define amdgpu_kernel void @smrd_sgpr_imm() { ret void }12...13---14 15name: smrd_imm16legalized: true17regBankSelected: true18 19# GCN: body:20# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr121 22# Immediate offset:23# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 024# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 025 26# Max immediate offset for SI27# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 028# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 029 30# Immediate overflow for SI31# SI: [[K1024:%[0-9]+]]:sreg_32 = S_MOV_B32 102432# SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 033# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 034# VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 035 36# Max immediate offset for VI37# SI: [[K1048572:%[0-9]+]]:sreg_32 = S_MOV_B32 104857238# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 26214339# VI: S_LOAD_DWORD_IMM [[PTR]], 104857240 41#42# Immediate overflow for VI43# SIVI: [[K1048576:%[0-9]+]]:sreg_32 = S_MOV_B32 104857644# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 045# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 046 47# Max immediate for CI48# SIVI: [[K:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1717986918049# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub050# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub051# SIVI-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]52# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub153# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub154# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]55# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub156# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 057# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 058 59# Immediate overflow for CI60# GCN: [[K:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 1717986918461# GCN-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub062# GCN-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub063# GCN-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]64# GCN-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub165# GCN-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub166# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]67# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub168# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 069 70# Max 32-bit byte offset71# SIVI: [[K4294967292:%[0-9]+]]:sreg_32 = S_MOV_B32 429496729272# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 073# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 074 75# Overflow 32-bit byte offset76# SIVI: [[K:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO 429496729677# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sreg_32 = COPY [[K]].sub078# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub079# SIVI-DAG: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]80# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sreg_32 = COPY [[K]].sub181# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sreg_32 = COPY [[PTR]].sub182# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]83# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64_xexec = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub184# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 085# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 086 87# Pointer loads88# GCN: [[AS0:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %089# GCN: $sgpr0_sgpr1 = COPY [[AS0]]90# GCN: [[AS1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %091# GCN: $sgpr0_sgpr1 = COPY [[AS1]]92# GCN: [[AS4:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %093# GCN: $sgpr0_sgpr1 = COPY [[AS4]]94 95body: |96 bb.0:97 liveins: $sgpr0_sgpr198 99 %0:sgpr(p4) = COPY $sgpr0_sgpr1100 101 %1:sgpr(s64) = G_CONSTANT i64 4102 %2:sgpr(p4) = G_PTR_ADD %0, %1103 %3:sgpr(s32) = G_LOAD %2 :: (load (s32) from %ir.const0, addrspace 4)104 $sgpr0 = COPY %3105 106 %4:sgpr(s64) = G_CONSTANT i64 1020107 %5:sgpr(p4) = G_PTR_ADD %0, %4108 %6:sgpr(s32) = G_LOAD %5 :: (load (s32) from %ir.const0, addrspace 4)109 $sgpr0 = COPY %6110 111 %7:sgpr(s64) = G_CONSTANT i64 1024112 %8:sgpr(p4) = G_PTR_ADD %0, %7113 %9:sgpr(s32) = G_LOAD %8 :: (load (s32) from %ir.const0, addrspace 4)114 $sgpr0 = COPY %9115 116 %10:sgpr(s64) = G_CONSTANT i64 1048572117 %11:sgpr(p4) = G_PTR_ADD %0, %10118 %12:sgpr(s32) = G_LOAD %11 :: (load (s32) from %ir.const0, addrspace 4)119 $sgpr0 = COPY %12120 121 %13:sgpr(s64) = G_CONSTANT i64 1048576122 %14:sgpr(p4) = G_PTR_ADD %0, %13123 %15:sgpr(s32) = G_LOAD %14 :: (load (s32) from %ir.const0, addrspace 4)124 $sgpr0 = COPY %15125 126 %16:sgpr(s64) = G_CONSTANT i64 17179869180127 %17:sgpr(p4) = G_PTR_ADD %0, %16128 %18:sgpr(s32) = G_LOAD %17 :: (load (s32) from %ir.const0, addrspace 4)129 $sgpr0 = COPY %18130 131 %19:sgpr(s64) = G_CONSTANT i64 17179869184132 %20:sgpr(p4) = G_PTR_ADD %0, %19133 %21:sgpr(s32) = G_LOAD %20 :: (load (s32) from %ir.const0, addrspace 4)134 $sgpr0 = COPY %21135 136 %22:sgpr(s64) = G_CONSTANT i64 4294967292137 %23:sgpr(p4) = G_PTR_ADD %0, %22138 %24:sgpr(s32) = G_LOAD %23 :: (load (s32) from %ir.const0, addrspace 4)139 $sgpr0 = COPY %24140 141 %25:sgpr(s64) = G_CONSTANT i64 4294967296142 %26:sgpr(p4) = G_PTR_ADD %0, %25143 %27:sgpr(s32) = G_LOAD %26 :: (load (s32) from %ir.const0, addrspace 4)144 $sgpr0 = COPY %27145 146 %28:sgpr(p0) = G_LOAD %0 :: (load (p0) from %ir.const0, addrspace 4)147 $sgpr0_sgpr1 = COPY %28148 149 %29:sgpr(p1) = G_LOAD %0 :: (load (p1) from %ir.const0, addrspace 4)150 $sgpr0_sgpr1 = COPY %29151 152 %30:sgpr(p4) = G_LOAD %0 :: (load (p4) from %ir.const0, addrspace 4)153 $sgpr0_sgpr1 = COPY %30154 155...156---157 158name: smrd_wide159legalized: true160regBankSelected: true161 162body: |163 bb.0:164 liveins: $sgpr0_sgpr1, $vgpr2_vgpr3165 %0:sgpr(p4) = COPY $sgpr0_sgpr1166 %1:sgpr(p1) = COPY $sgpr2_sgpr3167 168 ; CHECK: [[CONSTANT_PTR:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1169 ; CHECK: [[GLOBAL_PTR:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3170 ; CHECK: s_load_dwordx8 [[CONSTANT_PTR]]171 %2:sgpr(<8 x s32>) = G_LOAD %0 :: (load (<8 x s32>), addrspace 4)172 $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %2173 174 ; CHECK: s_load_dwordx16 [[CONSTANT_PTR]]175 %3:sgpr(<16 x s32>) = G_LOAD %0 :: (load (<16 x s32>), addrspace 4)176 $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %3177 178 ; CHECK: s_load_dwordx8 [[GLOBAL_PTR]]179 %4:sgpr(<8 x s32>) = G_LOAD %1 :: (load (<8 x s32>), addrspace 1)180 $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7 = COPY %4181 182 ; CHECK s_load_dwordx16 [[GLOBAL_PTR]]183 %5:sgpr(<16 x s32>) = G_LOAD %1 :: (load (<16 x s32>), addrspace 1)184 $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %5185...186 187 188# Test a load of an offset from a constant base address189# GCN-LABEL: name: constant_address_positive{{$}}190# GCN: %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 44191 192# VI: %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 64, 0 :: (dereferenceable invariant load (s32), addrspace 4)193# SICI: %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0 :: (dereferenceable invariant load (s32), addrspace 4)194 195---196 197name: constant_address_positive198legalized: true199regBankSelected: true200 201body: |202 bb.0:203 liveins: $sgpr0_sgpr1, $vgpr2_vgpr3204 %0:sgpr(p4) = G_CONSTANT i64 44205 %1:sgpr(s64) = G_CONSTANT i64 64206 %2:sgpr(p4) = G_PTR_ADD %0, %1207 %3:sgpr(s32) = G_LOAD %2 :: (dereferenceable invariant load (s32), align 4, addrspace 4)208 S_ENDPGM 0, implicit %3209...210 211---212 213# Test a load with a register offset.214# GCN-LABEL: name: smrd_sgpr{{$}}215# SICI: S_LOAD_DWORD_SGPR %0, %1, 0216# VI: S_LOAD_DWORD_SGPR %0, %1, 0217# GFX9: S_LOAD_DWORD_SGPR_IMM %0, %1, 0, 0218 219name: smrd_sgpr220legalized: true221regBankSelected: true222 223body: |224 bb.0:225 liveins: $sgpr0_sgpr1, $sgpr2226 %0:sgpr(p4) = COPY $sgpr0_sgpr1227 %1:sgpr(s32) = COPY $sgpr2228 %2:sgpr(s64) = G_ZEXT %1:sgpr(s32)229 %4:sgpr(p4) = G_PTR_ADD %0, %2230 %5:sgpr(s32) = G_LOAD %4 :: (dereferenceable invariant load (s32), align 4, addrspace 4)231 S_ENDPGM 0, implicit %5232...233 234---235 236# Test a load with a (register + immediate) offset.237# GCN-LABEL: name: smrd_sgpr_imm{{$}}238# GFX9-DAG: %[[BASE:.*]]:sreg_64 = COPY $sgpr0_sgpr1239# GFX9-DAG: %[[OFFSET:.*]]:sreg_32 = COPY $sgpr2240# GFX9: S_LOAD_DWORD_SGPR_IMM %[[BASE]], %[[OFFSET]], 16,241 242name: smrd_sgpr_imm243legalized: true244regBankSelected: true245 246body: |247 bb.0:248 liveins: $sgpr0_sgpr1, $sgpr2249 %0:sgpr(p4) = COPY $sgpr0_sgpr1250 %1:sgpr(s32) = COPY $sgpr2251 %2:sgpr(s64) = G_ZEXT %1:sgpr(s32)252 %4:sgpr(p4) = G_PTR_ADD %0, %2253 %5:sgpr(s64) = G_CONSTANT i64 16254 %6:sgpr(p4) = G_PTR_ADD %4, %5255 %7:sgpr(s32) = G_LOAD %6 :: (dereferenceable invariant load (s32), align 4, addrspace 4)256 S_ENDPGM 0, implicit %7257...258