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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX1100 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX1150 %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX12 %s6 7---8name: mad_u64_u32_vvv9legalized: true10regBankSelected: true11 12body: |13 bb.0:14 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr315 ; GFX10-LABEL: name: mad_u64_u32_vvv16 ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr317 ; GFX10-NEXT: {{ $}}18 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr019 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr120 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr321 ; GFX10-NEXT: [[V_MAD_U64_U32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_U64_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_U64_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec22 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MAD_U64_U32_e64_]], implicit [[V_MAD_U64_U32_e64_1]]23 ;24 ; GFX1100-LABEL: name: mad_u64_u32_vvv25 ; GFX1100: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr326 ; GFX1100-NEXT: {{ $}}27 ; GFX1100-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr028 ; GFX1100-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr129 ; GFX1100-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr330 ; GFX1100-NEXT: [[V_MAD_U64_U32_gfx11_e64_:%[0-9]+]]:vreg_64, [[V_MAD_U64_U32_gfx11_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_U64_U32_gfx11_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec31 ; GFX1100-NEXT: S_ENDPGM 0, implicit [[V_MAD_U64_U32_gfx11_e64_]], implicit [[V_MAD_U64_U32_gfx11_e64_1]]32 ;33 ; GFX1150-LABEL: name: mad_u64_u32_vvv34 ; GFX1150: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr335 ; GFX1150-NEXT: {{ $}}36 ; GFX1150-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr037 ; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr138 ; GFX1150-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr339 ; GFX1150-NEXT: [[V_MAD_U64_U32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_U64_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_U64_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec40 ; GFX1150-NEXT: S_ENDPGM 0, implicit [[V_MAD_U64_U32_e64_]], implicit [[V_MAD_U64_U32_e64_1]]41 ;42 ; GFX12-LABEL: name: mad_u64_u32_vvv43 ; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr344 ; GFX12-NEXT: {{ $}}45 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr046 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr147 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr348 ; GFX12-NEXT: [[V_MAD_U64_U32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_U64_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_U64_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec49 ; GFX12-NEXT: S_ENDPGM 0, implicit [[V_MAD_U64_U32_e64_]], implicit [[V_MAD_U64_U32_e64_1]]50 %0:vgpr(s32) = COPY $vgpr051 %1:vgpr(s32) = COPY $vgpr152 %2:vgpr(s32) = COPY $vgpr253 %3:vgpr(s32) = COPY $vgpr354 %4:vgpr(s64) = G_MERGE_VALUES %2, %355 %5:vgpr(s64), %6:vcc(s1) = G_AMDGPU_MAD_U64_U32 %0, %1, %356 S_ENDPGM 0, implicit %5, implicit %657...58 59---60name: mad_i64_i32_vvv61legalized: true62regBankSelected: true63 64body: |65 bb.0:66 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr367 ; GFX10-LABEL: name: mad_i64_i32_vvv68 ; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr369 ; GFX10-NEXT: {{ $}}70 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr071 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr172 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr373 ; GFX10-NEXT: [[V_MAD_I64_I32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_I64_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec74 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_MAD_I64_I32_e64_]], implicit [[V_MAD_I64_I32_e64_1]]75 ;76 ; GFX1100-LABEL: name: mad_i64_i32_vvv77 ; GFX1100: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr378 ; GFX1100-NEXT: {{ $}}79 ; GFX1100-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr080 ; GFX1100-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr181 ; GFX1100-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr382 ; GFX1100-NEXT: [[V_MAD_I64_I32_gfx11_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_gfx11_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_I64_I32_gfx11_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec83 ; GFX1100-NEXT: S_ENDPGM 0, implicit [[V_MAD_I64_I32_gfx11_e64_]], implicit [[V_MAD_I64_I32_gfx11_e64_1]]84 ;85 ; GFX1150-LABEL: name: mad_i64_i32_vvv86 ; GFX1150: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr387 ; GFX1150-NEXT: {{ $}}88 ; GFX1150-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr089 ; GFX1150-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr190 ; GFX1150-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr391 ; GFX1150-NEXT: [[V_MAD_I64_I32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_I64_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec92 ; GFX1150-NEXT: S_ENDPGM 0, implicit [[V_MAD_I64_I32_e64_]], implicit [[V_MAD_I64_I32_e64_1]]93 ;94 ; GFX12-LABEL: name: mad_i64_i32_vvv95 ; GFX12: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr396 ; GFX12-NEXT: {{ $}}97 ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr098 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr199 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3100 ; GFX12-NEXT: [[V_MAD_I64_I32_e64_:%[0-9]+]]:vreg_64, [[V_MAD_I64_I32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_MAD_I64_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], 0, implicit $exec101 ; GFX12-NEXT: S_ENDPGM 0, implicit [[V_MAD_I64_I32_e64_]], implicit [[V_MAD_I64_I32_e64_1]]102 %0:vgpr(s32) = COPY $vgpr0103 %1:vgpr(s32) = COPY $vgpr1104 %2:vgpr(s32) = COPY $vgpr2105 %3:vgpr(s32) = COPY $vgpr3106 %4:vgpr(s64) = G_MERGE_VALUES %2, %3107 %5:vgpr(s64), %6:vcc(s1) = G_AMDGPU_MAD_I64_I32 %0, %1, %3108 S_ENDPGM 0, implicit %5, implicit %6109...110