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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s3 4---5name: umed3_s32_vvv6legalized: true7regBankSelected: true8 9body: |10 bb.0:11 liveins: $vgpr0, $vgpr1, $vgpr212 13 ; GFX6-LABEL: name: umed3_s32_vvv14 ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr215 ; GFX6-NEXT: {{ $}}16 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr017 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr118 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr219 ; GFX6-NEXT: [[V_MED3_U32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec20 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_U32_e64_]]21 %0:vgpr(s32) = COPY $vgpr022 %1:vgpr(s32) = COPY $vgpr123 %2:vgpr(s32) = COPY $vgpr224 %3:vgpr(s32) = G_UMAX %0, %125 %4:vgpr(s32) = G_UMIN %0, %126 %5:vgpr(s32) = G_UMAX %4, %227 %6:vgpr(s32) = G_UMIN %3, %528 S_ENDPGM 0, implicit %629...30 31---32 33name: umed3_s32_sss34legalized: true35regBankSelected: true36 37body: |38 bb.0:39 liveins: $sgpr0, $sgpr1, $sgpr240 41 ; GFX6-LABEL: name: umed3_s32_sss42 ; GFX6: liveins: $sgpr0, $sgpr1, $sgpr243 ; GFX6-NEXT: {{ $}}44 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr045 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr146 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr247 ; GFX6-NEXT: [[S_MAX_U32_:%[0-9]+]]:sreg_32 = S_MAX_U32 [[COPY]], [[COPY1]], implicit-def dead $scc48 ; GFX6-NEXT: [[S_MIN_U32_:%[0-9]+]]:sreg_32 = S_MIN_U32 [[COPY]], [[COPY1]], implicit-def dead $scc49 ; GFX6-NEXT: [[S_MAX_U32_1:%[0-9]+]]:sreg_32 = S_MAX_U32 [[S_MIN_U32_]], [[COPY2]], implicit-def dead $scc50 ; GFX6-NEXT: [[S_MIN_U32_1:%[0-9]+]]:sreg_32 = S_MIN_U32 [[S_MAX_U32_]], [[S_MAX_U32_1]], implicit-def dead $scc51 ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_MIN_U32_1]]52 %0:sgpr(s32) = COPY $sgpr053 %1:sgpr(s32) = COPY $sgpr154 %2:sgpr(s32) = COPY $sgpr255 %3:sgpr(s32) = G_UMAX %0, %156 %4:sgpr(s32) = G_UMIN %0, %157 %5:sgpr(s32) = G_UMAX %4, %258 %6:sgpr(s32) = G_UMIN %3, %559 S_ENDPGM 0, implicit %660...61 62---63name: umed3_s32_vvv_multiuse064legalized: true65regBankSelected: true66 67body: |68 bb.0:69 liveins: $vgpr0, $vgpr1, $vgpr270 71 ; GFX6-LABEL: name: umed3_s32_vvv_multiuse072 ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr273 ; GFX6-NEXT: {{ $}}74 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr075 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr176 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr277 ; GFX6-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec78 ; GFX6-NEXT: [[V_MED3_U32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec79 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_U32_e64_]], implicit [[V_MAX_U32_e64_]]80 %0:vgpr(s32) = COPY $vgpr081 %1:vgpr(s32) = COPY $vgpr182 %2:vgpr(s32) = COPY $vgpr283 %3:vgpr(s32) = G_UMAX %0, %184 %4:vgpr(s32) = G_UMIN %0, %185 %5:vgpr(s32) = G_UMAX %4, %286 %6:vgpr(s32) = G_UMIN %3, %587 S_ENDPGM 0, implicit %6, implicit %388...89 90---91name: umed3_s32_vvv_multiuse192legalized: true93regBankSelected: true94 95body: |96 bb.0:97 liveins: $vgpr0, $vgpr1, $vgpr298 99 ; GFX6-LABEL: name: umed3_s32_vvv_multiuse1100 ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2101 ; GFX6-NEXT: {{ $}}102 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0103 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1104 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2105 ; GFX6-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec106 ; GFX6-NEXT: [[V_MED3_U32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec107 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_U32_e64_]], implicit [[V_MIN_U32_e64_]]108 %0:vgpr(s32) = COPY $vgpr0109 %1:vgpr(s32) = COPY $vgpr1110 %2:vgpr(s32) = COPY $vgpr2111 %3:vgpr(s32) = G_UMAX %0, %1112 %4:vgpr(s32) = G_UMIN %0, %1113 %5:vgpr(s32) = G_UMAX %4, %2114 %6:vgpr(s32) = G_UMIN %3, %5115 S_ENDPGM 0, implicit %6, implicit %4116...117 118---119name: umed3_s32_vvv_multiuse2120legalized: true121regBankSelected: true122 123body: |124 bb.0:125 liveins: $vgpr0, $vgpr1, $vgpr2126 127 ; GFX6-LABEL: name: umed3_s32_vvv_multiuse2128 ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2129 ; GFX6-NEXT: {{ $}}130 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0131 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1132 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2133 ; GFX6-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec134 ; GFX6-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[V_MIN_U32_e64_]], [[COPY2]], implicit $exec135 ; GFX6-NEXT: [[V_MED3_U32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec136 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_U32_e64_]], implicit [[V_MAX_U32_e64_]]137 %0:vgpr(s32) = COPY $vgpr0138 %1:vgpr(s32) = COPY $vgpr1139 %2:vgpr(s32) = COPY $vgpr2140 %3:vgpr(s32) = G_UMAX %0, %1141 %4:vgpr(s32) = G_UMIN %0, %1142 %5:vgpr(s32) = G_UMAX %4, %2143 %6:vgpr(s32) = G_UMIN %3, %5144 S_ENDPGM 0, implicit %6, implicit %5145...146 147---148name: smed3_s32_vvv_reuse_bounds149legalized: true150regBankSelected: true151 152body: |153 bb.0:154 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3155 156 ; GFX6-LABEL: name: smed3_s32_vvv_reuse_bounds157 ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3158 ; GFX6-NEXT: {{ $}}159 ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0160 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1161 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2162 ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3163 ; GFX6-NEXT: [[V_MED3_U32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec164 ; GFX6-NEXT: [[V_MED3_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY3]], implicit $exec165 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_U32_e64_]], implicit [[V_MED3_U32_e64_1]]166 %0:vgpr(s32) = COPY $vgpr0167 %1:vgpr(s32) = COPY $vgpr1168 %2:vgpr(s32) = COPY $vgpr2169 %3:vgpr(s32) = COPY $vgpr3170 %4:vgpr(s32) = G_UMAX %0, %1171 %5:vgpr(s32) = G_UMIN %0, %1172 %6:vgpr(s32) = G_UMIN %2, %4173 %7:vgpr(s32) = G_UMAX %6, %5174 %8:vgpr(s32) = G_UMIN %3, %4175 %9:vgpr(s32) = G_UMAX %8, %5176 S_ENDPGM 0, implicit %7, implicit %9177...178