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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s3 4---5name: v_s_exp_f326legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0:11 liveins: $sgpr012 13 ; CHECK-LABEL: name: v_s_exp_f3214 ; CHECK: liveins: $sgpr015 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr017 ; CHECK-NEXT: [[V_S_EXP_F32_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec18 ; CHECK-NEXT: $vgpr0 = COPY [[V_S_EXP_F32_e64_]]19 %0:sgpr(s32) = COPY $sgpr020 %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %021 $vgpr0 = COPY %1(s32)22 23...24---25name: v_s_exp_f1626legalized: true27regBankSelected: true28tracksRegLiveness: true29body: |30 bb.0:31 liveins: $sgpr032 33 ; CHECK-LABEL: name: v_s_exp_f1634 ; CHECK: liveins: $sgpr035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr037 ; CHECK-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_EXP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec38 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_EXP_F16_e64_]]39 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]40 %0:sgpr(s32) = COPY $sgpr041 %1:sgpr(s16) = G_TRUNC %0(s32)42 %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.exp2), %143 %3:sgpr(s32) = G_ANYEXT %2(s16)44 $vgpr0 = COPY %3(s32)45 46...47---48name: v_s_log_f3249legalized: true50regBankSelected: true51tracksRegLiveness: true52body: |53 bb.0:54 liveins: $sgpr055 56 ; CHECK-LABEL: name: v_s_log_f3257 ; CHECK: liveins: $sgpr058 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr060 ; CHECK-NEXT: [[V_S_LOG_F32_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_LOG_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec61 ; CHECK-NEXT: $vgpr0 = COPY [[V_S_LOG_F32_e64_]]62 %0:sgpr(s32) = COPY $sgpr063 %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), %064 $vgpr0 = COPY %1(s32)65 66...67---68name: v_s_log_f1669legalized: true70regBankSelected: true71tracksRegLiveness: true72body: |73 bb.0:74 liveins: $sgpr075 76 ; CHECK-LABEL: name: v_s_log_f1677 ; CHECK: liveins: $sgpr078 ; CHECK-NEXT: {{ $}}79 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr080 ; CHECK-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_LOG_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec81 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_LOG_F16_e64_]]82 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]83 %0:sgpr(s32) = COPY $sgpr084 %1:sgpr(s16) = G_TRUNC %0(s32)85 %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.log), %186 %3:sgpr(s32) = G_ANYEXT %2(s16)87 $vgpr0 = COPY %3(s32)88 89...90---91name: v_s_rcp_f3292legalized: true93regBankSelected: true94tracksRegLiveness: true95body: |96 bb.0:97 liveins: $sgpr098 99 ; CHECK-LABEL: name: v_s_rcp_f32100 ; CHECK: liveins: $sgpr0101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0103 ; CHECK-NEXT: [[V_S_RCP_F32_e64_:%[0-9]+]]:sreg_32_xexec = nnan ninf nsz arcp contract afn reassoc nofpexcept V_S_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec104 ; CHECK-NEXT: $vgpr0 = COPY [[V_S_RCP_F32_e64_]]105 %0:sgpr(s32) = COPY $sgpr0106 %1:sgpr(s32) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0(s32)107 $vgpr0 = COPY %1(s32)108 109...110---111name: v_s_rcp_f16112legalized: true113regBankSelected: true114tracksRegLiveness: true115body: |116 bb.0:117 liveins: $sgpr0118 119 ; CHECK-LABEL: name: v_s_rcp_f16120 ; CHECK: liveins: $sgpr0121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0123 ; CHECK-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sreg_32_xexec = nnan ninf nsz arcp contract afn reassoc nofpexcept V_S_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec124 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_RCP_F16_e64_]]125 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]126 %0:sgpr(s32) = COPY $sgpr0127 %1:sgpr(s16) = G_TRUNC %0(s32)128 %2:sgpr(s16) = nnan ninf nsz arcp contract afn reassoc G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1(s16)129 %3:sgpr(s32) = G_ANYEXT %2(s16)130 $vgpr0 = COPY %3(s32)131 132...133---134name: v_s_rsq_f32135legalized: true136regBankSelected: true137tracksRegLiveness: true138body: |139 bb.0:140 liveins: $sgpr0141 142 ; CHECK-LABEL: name: v_s_rsq_f32143 ; CHECK: liveins: $sgpr0144 ; CHECK-NEXT: {{ $}}145 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0146 ; CHECK-NEXT: [[V_S_RSQ_F32_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec147 ; CHECK-NEXT: $vgpr0 = COPY [[V_S_RSQ_F32_e64_]]148 %0:sgpr(s32) = COPY $sgpr0149 %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0(s32)150 $vgpr0 = COPY %1(s32)151 152...153---154name: v_s_rsq_f16155legalized: true156regBankSelected: true157tracksRegLiveness: true158body: |159 bb.0:160 liveins: $sgpr0161 162 ; CHECK-LABEL: name: v_s_rsq_f16163 ; CHECK: liveins: $sgpr0164 ; CHECK-NEXT: {{ $}}165 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0166 ; CHECK-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec167 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_RSQ_F16_e64_]]168 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]169 %0:sgpr(s32) = COPY $sgpr0170 %1:sgpr(s16) = G_TRUNC %0(s32)171 %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1(s16)172 %3:sgpr(s32) = G_ANYEXT %2(s16)173 $vgpr0 = COPY %3(s32)174 175...176---177name: v_s_sqrt_f32178legalized: true179regBankSelected: true180tracksRegLiveness: true181body: |182 bb.0:183 liveins: $sgpr0184 185 ; CHECK-LABEL: name: v_s_sqrt_f32186 ; CHECK: liveins: $sgpr0187 ; CHECK-NEXT: {{ $}}188 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0189 ; CHECK-NEXT: [[V_S_SQRT_F32_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_SQRT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec190 ; CHECK-NEXT: $vgpr0 = COPY [[V_S_SQRT_F32_e64_]]191 %0:sgpr(s32) = COPY $sgpr0192 %1:sgpr(s32) = G_FSQRT %0193 $vgpr0 = COPY %1(s32)194 195...196---197name: v_s_sqrt_f16198legalized: true199regBankSelected: true200tracksRegLiveness: true201body: |202 bb.0:203 liveins: $sgpr0204 205 ; CHECK-LABEL: name: v_s_sqrt_f16206 ; CHECK: liveins: $sgpr0207 ; CHECK-NEXT: {{ $}}208 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0209 ; CHECK-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec210 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_SQRT_F16_e64_]]211 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]212 %0:sgpr(s32) = COPY $sgpr0213 %1:sgpr(s16) = G_TRUNC %0(s32)214 %2:sgpr(s16) = G_FSQRT %1215 %3:sgpr(s32) = G_ANYEXT %2(s16)216 $vgpr0 = COPY %3(s32)217 218...219---220name: v_amdgcn_sqrt_f32221legalized: true222regBankSelected: true223tracksRegLiveness: true224body: |225 bb.0:226 liveins: $sgpr0227 228 ; CHECK-LABEL: name: v_amdgcn_sqrt_f32229 ; CHECK: liveins: $sgpr0230 ; CHECK-NEXT: {{ $}}231 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0232 ; CHECK-NEXT: [[V_S_SQRT_F32_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_SQRT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec233 ; CHECK-NEXT: $vgpr0 = COPY [[V_S_SQRT_F32_e64_]]234 %0:sgpr(s32) = COPY $sgpr0235 %1:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0(s32)236 $vgpr0 = COPY %1(s32)237 238...239---240name: v_amdgcn_sqrt_f16241legalized: true242regBankSelected: true243tracksRegLiveness: true244body: |245 bb.0:246 liveins: $sgpr0247 248 ; CHECK-LABEL: name: v_amdgcn_sqrt_f16249 ; CHECK: liveins: $sgpr0250 ; CHECK-NEXT: {{ $}}251 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0252 ; CHECK-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sreg_32_xexec = nofpexcept V_S_SQRT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec253 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[V_S_SQRT_F16_e64_]]254 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]]255 %0:sgpr(s32) = COPY $sgpr0256 %1:sgpr(s16) = G_TRUNC %0(s32)257 %2:sgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %1(s16)258 %3:sgpr(s32) = G_ANYEXT %2(s16)259 $vgpr0 = COPY %3(s32)260 261...262