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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s3 4# The only instruction selection cases for G_SBFX/G_UBFX are the 64-bit5# vector versions. All other versions, scalar and 32-bit vector, are6# expanded during register bank selection.7 8---9name: sbfx_s32_vii10legalized: true11regBankSelected: true12tracksRegLiveness: true13body: |14 bb.0:15 liveins: $vgpr016 ; CHECK-LABEL: name: sbfx_s32_vii17 ; CHECK: liveins: $vgpr018 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr020 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec21 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 10, implicit $exec22 ; CHECK-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], implicit $exec23 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFE_I32_e64_]]24 %0:vgpr(s32) = COPY $vgpr025 %1:vgpr(s32) = G_CONSTANT i32 226 %2:vgpr(s32) = G_CONSTANT i32 1027 %3:vgpr(s32) = G_SBFX %0, %1(s32), %228 S_ENDPGM 0, implicit %329...30 31---32name: sbfx_s32_vvv33legalized: true34regBankSelected: true35tracksRegLiveness: true36body: |37 bb.0:38 liveins: $vgpr0, $vgpr1, $vgpr239 ; CHECK-LABEL: name: sbfx_s32_vvv40 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr241 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr043 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr144 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr245 ; CHECK-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec46 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_BFE_I32_e64_]]47 %0:vgpr(s32) = COPY $vgpr048 %1:vgpr(s32) = COPY $vgpr149 %2:vgpr(s32) = COPY $vgpr250 %3:vgpr(s32) = G_SBFX %0, %1(s32), %251 S_ENDPGM 0, implicit %352...53