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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s6# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s7 8---9name: sub_s3210legalized: true11regBankSelected: true12tracksRegLiveness: true13 14body: |15 bb.0:16 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr417 18 19 ; GFX6-LABEL: name: sub_s3220 ; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr421 ; GFX6-NEXT: {{ $}}22 ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr023 ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr124 ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr025 ; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def dead $scc26 ; GFX6-NEXT: [[V_SUB_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_SUB_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_SUB_CO_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec27 ; GFX6-NEXT: [[V_SUB_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_SUB_CO_U32_e64_3:%[0-9]+]]:sreg_64 = V_SUB_CO_U32_e64 [[S_SUB_I32_]], [[V_SUB_CO_U32_e64_]], 0, implicit $exec28 ; GFX6-NEXT: [[V_SUB_CO_U32_e64_4:%[0-9]+]]:vgpr_32, dead [[V_SUB_CO_U32_e64_5:%[0-9]+]]:sreg_64 = V_SUB_CO_U32_e64 [[V_SUB_CO_U32_e64_2]], [[COPY2]], 0, implicit $exec29 ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_CO_U32_e64_4]]30 ;31 ; GFX9-LABEL: name: sub_s3232 ; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr433 ; GFX9-NEXT: {{ $}}34 ; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr035 ; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr136 ; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr037 ; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], [[COPY1]], implicit-def dead $scc38 ; GFX9-NEXT: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY2]], [[S_SUB_I32_]], 0, implicit $exec39 ; GFX9-NEXT: [[V_SUB_U32_e64_1:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[S_SUB_I32_]], [[V_SUB_U32_e64_]], 0, implicit $exec40 ; GFX9-NEXT: [[V_SUB_U32_e64_2:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[V_SUB_U32_e64_1]], [[COPY2]], 0, implicit $exec41 ; GFX9-NEXT: S_ENDPGM 0, implicit [[V_SUB_U32_e64_2]]42 %0:sgpr(s32) = COPY $sgpr043 %1:sgpr(s32) = COPY $sgpr144 %2:vgpr(s32) = COPY $vgpr045 %3:vgpr(p1) = COPY $vgpr3_vgpr446 %4:sgpr(s32) = G_CONSTANT i32 147 %5:sgpr(s32) = G_CONSTANT i32 409648 49 %6:sgpr(s32) = G_SUB %0, %150 51 %7:vgpr(s32) = G_SUB %2, %652 53 %8:vgpr(s32) = G_SUB %6, %754 55 %9:vgpr(s32) = G_SUB %8, %256 57 S_ENDPGM 0, implicit %958 59...60