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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s4 5# These violate the constant bus restriction pre-gfx106 7---8name: uadde_s32_s1_vsv9legalized: true10regBankSelected: true11 12body: |13 bb.0:14 liveins: $sgpr0, $vgpr015 16 ; GFX10-LABEL: name: uadde_s32_s1_vsv17 ; GFX10: liveins: $sgpr0, $vgpr018 ; GFX10-NEXT: {{ $}}19 ; GFX10-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr020 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr021 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr222 ; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec23 ; GFX10-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec24 ; GFX10-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec25 ; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec26 ; GFX10-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec27 ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec28 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]29 %0:sgpr(s32) = COPY $sgpr030 %1:vgpr(s32) = COPY $vgpr031 %2:vgpr(s32) = COPY $vgpr232 %3:vgpr(s32) = G_CONSTANT i32 033 %4:vcc(s1) = G_ICMP intpred(eq), %2, %334 %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %435 %7:vgpr(s32) = G_CONSTANT i32 036 %8:vgpr(s32) = G_CONSTANT i32 137 %9:vgpr(s32) = G_SELECT %6, %7, %838 S_ENDPGM 0, implicit %5, implicit %939...40 41---42name: uadde_s32_s1_vvs43legalized: true44regBankSelected: true45 46body: |47 bb.0:48 liveins: $sgpr0, $vgpr049 50 ; GFX10-LABEL: name: uadde_s32_s1_vvs51 ; GFX10: liveins: $sgpr0, $vgpr052 ; GFX10-NEXT: {{ $}}53 ; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr054 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr055 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr256 ; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec57 ; GFX10-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY2]], [[V_MOV_B32_e32_]], implicit $exec58 ; GFX10-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADDC_U32_e64 [[COPY]], [[COPY1]], [[V_CMP_EQ_U32_e64_]], 0, implicit $exec59 ; GFX10-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec60 ; GFX10-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec61 ; GFX10-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_MOV_B32_e32_2]], 0, [[V_MOV_B32_e32_1]], [[V_ADDC_U32_e64_1]], implicit $exec62 ; GFX10-NEXT: S_ENDPGM 0, implicit [[V_ADDC_U32_e64_]], implicit [[V_CNDMASK_B32_e64_]]63 %0:vgpr(s32) = COPY $vgpr064 %1:sgpr(s32) = COPY $sgpr065 %2:vgpr(s32) = COPY $vgpr266 %3:vgpr(s32) = G_CONSTANT i32 067 %4:vcc(s1) = G_ICMP intpred(eq), %2, %368 %5:vgpr(s32), %6:vcc(s1) = G_UADDE %0, %1, %469 %7:vgpr(s32) = G_CONSTANT i32 070 %8:vgpr(s32) = G_CONSTANT i32 171 %9:vgpr(s32) = G_SELECT %6, %7, %872 S_ENDPGM 0, implicit %5, implicit %973...74