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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 22; RUN: llc --global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1100 -stop-after=irtranslator %s -o - | FileCheck %s --check-prefix=GFX113; RUN: llc --global-isel=1 -mtriple=amdgcn--amdpal -mcpu=gfx1030 -stop-after=irtranslator %s -o - | FileCheck %s --check-prefix=GFX104 5declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 })6declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 })7declare void @llvm.amdgcn.cs.chain(ptr, i32, <3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }, i32, ...) noreturn8 9define amdgpu_cs_chain void @chain_call(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr) {10 ; GFX11-LABEL: name: chain_call11 ; GFX11: bb.1 (%ir-block.0):12 ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr8, $vgpr9, $vgpr10, $vgpr1113 ; GFX11-NEXT: {{ $}}14 ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr015 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr116 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr217 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)18 ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr819 ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(p5) = COPY $vgpr920 ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr1021 ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr1122 ; GFX11-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @callee23 ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -124 ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 025 ; GFX11-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee26 ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)27 ; GFX11-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)28 ; GFX11-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)29 ; GFX11-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)30 ; GFX11-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)31 ; GFX11-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32)32 ; GFX11-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32)33 ; GFX11-NEXT: $vgpr8 = COPY [[COPY3]](s32)34 ; GFX11-NEXT: $vgpr9 = COPY [[COPY4]](p5)35 ; GFX11-NEXT: $vgpr10 = COPY [[COPY5]](s32)36 ; GFX11-NEXT: $vgpr11 = COPY [[COPY6]](s32)37 ; GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[GV1]](p0), @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr1138 ;39 ; GFX10-LABEL: name: chain_call40 ; GFX10: bb.1 (%ir-block.0):41 ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr8, $vgpr9, $vgpr10, $vgpr1142 ; GFX10-NEXT: {{ $}}43 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr044 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr145 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr246 ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)47 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr848 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(p5) = COPY $vgpr949 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr1050 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr1151 ; GFX10-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @callee52 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -153 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 054 ; GFX10-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee55 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)56 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)57 ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)58 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)59 ; GFX10-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)60 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32)61 ; GFX10-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32)62 ; GFX10-NEXT: $vgpr8 = COPY [[COPY3]](s32)63 ; GFX10-NEXT: $vgpr9 = COPY [[COPY4]](p5)64 ; GFX10-NEXT: $vgpr10 = COPY [[COPY5]](s32)65 ; GFX10-NEXT: $vgpr11 = COPY [[COPY6]](s32)66 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr48_sgpr49_sgpr50_sgpr5167 ; GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]](<4 x s32>)68 ; GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[GV1]](p0), @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr5169 call void(ptr, i32, <3 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain(ptr @callee, i32 -1, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr, i32 0)70 unreachable71}72 73define amdgpu_cs_chain void @chain_preserve_call(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr) {74 ; GFX11-LABEL: name: chain_preserve_call75 ; GFX11: bb.1 (%ir-block.0):76 ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr8, $vgpr9, $vgpr10, $vgpr1177 ; GFX11-NEXT: {{ $}}78 ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr079 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr180 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr281 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)82 ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr883 ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(p5) = COPY $vgpr984 ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr1085 ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr1186 ; GFX11-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @callee_preserve87 ; GFX11-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -188 ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 089 ; GFX11-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee_preserve90 ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)91 ; GFX11-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)92 ; GFX11-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)93 ; GFX11-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)94 ; GFX11-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)95 ; GFX11-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32)96 ; GFX11-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32)97 ; GFX11-NEXT: $vgpr8 = COPY [[COPY3]](s32)98 ; GFX11-NEXT: $vgpr9 = COPY [[COPY4]](p5)99 ; GFX11-NEXT: $vgpr10 = COPY [[COPY5]](s32)100 ; GFX11-NEXT: $vgpr11 = COPY [[COPY6]](s32)101 ; GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[GV1]](p0), @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11102 ;103 ; GFX10-LABEL: name: chain_preserve_call104 ; GFX10: bb.1 (%ir-block.0):105 ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr8, $vgpr9, $vgpr10, $vgpr11106 ; GFX10-NEXT: {{ $}}107 ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0108 ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1109 ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2110 ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)111 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr8112 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(p5) = COPY $vgpr9113 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr10114 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr11115 ; GFX10-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @callee_preserve116 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1117 ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0118 ; GFX10-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee_preserve119 ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)120 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)121 ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)122 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)123 ; GFX10-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)124 ; GFX10-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32)125 ; GFX10-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32)126 ; GFX10-NEXT: $vgpr8 = COPY [[COPY3]](s32)127 ; GFX10-NEXT: $vgpr9 = COPY [[COPY4]](p5)128 ; GFX10-NEXT: $vgpr10 = COPY [[COPY5]](s32)129 ; GFX10-NEXT: $vgpr11 = COPY [[COPY6]](s32)130 ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr48_sgpr49_sgpr50_sgpr51131 ; GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]](<4 x s32>)132 ; GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[GV1]](p0), @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51133 call void(ptr, i32, <3 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) @llvm.amdgcn.cs.chain(ptr @callee_preserve, i32 -1, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr, i32 0)134 unreachable135}136 137 138