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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=irtranslator %s -o - | FileCheck %s3 4define amdgpu_vs void @test_f32_inreg(float inreg %arg0) {5 ; CHECK-LABEL: name: test_f32_inreg6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $sgpr28 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr210 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF11 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 012 ; CHECK-NEXT: S_ENDPGM 013 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #014 ret void15}16 17define amdgpu_vs void @test_f32(float %arg0) {18 ; CHECK-LABEL: name: test_f3219 ; CHECK: bb.1 (%ir-block.0):20 ; CHECK-NEXT: liveins: $vgpr021 ; CHECK-NEXT: {{ $}}22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr023 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF24 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 025 ; CHECK-NEXT: S_ENDPGM 026 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #027 ret void28}29 30define amdgpu_vs void @test_ptr2_inreg(ptr addrspace(4) inreg %arg0) {31 ; CHECK-LABEL: name: test_ptr2_inreg32 ; CHECK: bb.1 (%ir-block.0):33 ; CHECK-NEXT: liveins: $sgpr2, $sgpr334 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr236 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr337 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)38 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (volatile invariant load (s32) from %ir.arg0, addrspace 4)39 ; CHECK-NEXT: S_ENDPGM 040 %tmp0 = load volatile i32, ptr addrspace(4) %arg041 ret void42}43 44define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, ptr addrspace(4) inreg %arg1) {45 ; CHECK-LABEL: name: test_sgpr_alignment046 ; CHECK: bb.1 (%ir-block.0):47 ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr448 ; CHECK-NEXT: {{ $}}49 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr250 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr351 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr452 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)53 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF54 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (volatile invariant load (s32) from %ir.arg1, addrspace 4)55 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY]](s32), [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), 0, 056 ; CHECK-NEXT: S_ENDPGM 057 %tmp0 = load volatile i32, ptr addrspace(4) %arg158 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float poison, float poison, float poison, i1 false, i1 false) #059 ret void60}61 62define amdgpu_vs void @test_order(float inreg %arg0, float inreg %arg1, float %arg2, float %arg3) {63 ; CHECK-LABEL: name: test_order64 ; CHECK: bb.1 (%ir-block.0):65 ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr166 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr268 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr369 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr070 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr171 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 32, 15, [[COPY2]](s32), [[COPY]](s32), [[COPY3]](s32), [[COPY1]](s32), 0, 072 ; CHECK-NEXT: S_ENDPGM 073 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg2, float %arg0, float %arg3, float %arg1, i1 false, i1 false) #074 ret void75}76 77define amdgpu_vs <{ i32, i32 }> @ret_struct(i32 inreg %arg0, i32 inreg %arg1) {78 ; CHECK-LABEL: name: ret_struct79 ; CHECK: bb.1.main_body:80 ; CHECK-NEXT: liveins: $sgpr2, $sgpr381 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr283 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr384 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF85 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY]](s32)86 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)87 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)88 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)89 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr190main_body:91 %tmp0 = insertvalue <{ i32, i32 }> poison, i32 %arg0, 092 %tmp1 = insertvalue <{ i32, i32 }> %tmp0, i32 %arg1, 193 ret <{ i32, i32 }> %tmp194}95 96define amdgpu_vs i32 @non_void_ret() {97 ; CHECK-LABEL: name: non_void_ret98 ; CHECK: bb.1 (%ir-block.0):99 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0100 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[C]](s32)101 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)102 ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0103 ret i32 0104}105 106declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0107 108attributes #0 = { nounwind }109