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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx942 -O0 -stop-after=irtranslator -o - %s | FileCheck %s3 4define float @test_atomicrmw_fadd(ptr addrspace(3) %addr) {5 ; CHECK-LABEL: name: test_atomicrmw_fadd6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $vgpr08 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr010 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0011 ; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[C]] :: (load store seq_cst (s32) on %ir.addr, addrspace 3)12 ; CHECK-NEXT: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)13 ; CHECK-NEXT: SI_RETURN implicit $vgpr014 %oldval = atomicrmw fadd ptr addrspace(3) %addr, float 1.0 seq_cst15 ret float %oldval16}17 18define float @test_atomicrmw_fsub(ptr addrspace(3) %addr) {19 ; CHECK-LABEL: name: test_atomicrmw_fsub20 ; CHECK: bb.1 (%ir-block.0):21 ; CHECK-NEXT: successors: %bb.2(0x80000000)22 ; CHECK-NEXT: liveins: $vgpr023 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr025 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0026 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 027 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32) from %ir.addr, addrspace 3)28 ; CHECK-NEXT: G_BR %bb.229 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: bb.2.atomicrmw.start:31 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)32 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %16(s64), %bb.2, [[C1]](s64), %bb.134 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[LOAD]](s32), %bb.1, %14(s32), %bb.235 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[PHI1]], [[C]]36 ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[PHI1]], [[FSUB]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)37 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)38 ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)39 ; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.340 ; CHECK-NEXT: G_BR %bb.241 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: bb.3.atomicrmw.end:43 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32), %bb.244 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.245 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)46 ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](s32)47 ; CHECK-NEXT: SI_RETURN implicit $vgpr048 %oldval = atomicrmw fsub ptr addrspace(3) %addr, float 1.0 seq_cst49 ret float %oldval50}51 52define <2 x half> @test_atomicrmw_fadd_vector(ptr addrspace(3) %addr) {53 ; CHECK-LABEL: name: test_atomicrmw_fadd_vector54 ; CHECK: bb.1 (%ir-block.0):55 ; CHECK-NEXT: liveins: $vgpr056 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr058 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C0059 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)60 ; CHECK-NEXT: [[ATOMICRMW_FADD:%[0-9]+]]:_(<2 x s16>) = G_ATOMICRMW_FADD [[COPY]](p3), [[BUILD_VECTOR]] :: (load store seq_cst (<2 x s16>) on %ir.addr, addrspace 3)61 ; CHECK-NEXT: $vgpr0 = COPY [[ATOMICRMW_FADD]](<2 x s16>)62 ; CHECK-NEXT: SI_RETURN implicit $vgpr063 %oldval = atomicrmw fadd ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst64 ret <2 x half> %oldval65}66 67define <2 x half> @test_atomicrmw_fsub_vector(ptr addrspace(3) %addr) {68 ; CHECK-LABEL: name: test_atomicrmw_fsub_vector69 ; CHECK: bb.1 (%ir-block.0):70 ; CHECK-NEXT: successors: %bb.2(0x80000000)71 ; CHECK-NEXT: liveins: $vgpr072 ; CHECK-NEXT: {{ $}}73 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr074 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C0075 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)76 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 077 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)78 ; CHECK-NEXT: G_BR %bb.279 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: bb.2.atomicrmw.start:81 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)82 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %20(s64), %bb.2, [[C1]](s64), %bb.184 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %19(<2 x s16>), %bb.285 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(<2 x s16>) = G_FSUB [[PHI1]], [[BUILD_VECTOR]]86 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FSUB]](<2 x s16>)87 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)88 ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)89 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)90 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)91 ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)92 ; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.393 ; CHECK-NEXT: G_BR %bb.294 ; CHECK-NEXT: {{ $}}95 ; CHECK-NEXT: bb.3.atomicrmw.end:96 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.297 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.298 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)99 ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)100 ; CHECK-NEXT: SI_RETURN implicit $vgpr0101 %oldval = atomicrmw fsub ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst102 ret <2 x half> %oldval103}104 105define <2 x half> @test_atomicrmw_fmin_vector(ptr addrspace(3) %addr) {106 ; CHECK-LABEL: name: test_atomicrmw_fmin_vector107 ; CHECK: bb.1 (%ir-block.0):108 ; CHECK-NEXT: successors: %bb.2(0x80000000)109 ; CHECK-NEXT: liveins: $vgpr0110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0112 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00113 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)114 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0115 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)116 ; CHECK-NEXT: G_BR %bb.2117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: bb.2.atomicrmw.start:119 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %20(s64), %bb.2, [[C1]](s64), %bb.1122 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %19(<2 x s16>), %bb.2123 ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM [[PHI1]], [[BUILD_VECTOR]]124 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FMINNUM]](<2 x s16>)125 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)126 ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)127 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)128 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)129 ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)130 ; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3131 ; CHECK-NEXT: G_BR %bb.2132 ; CHECK-NEXT: {{ $}}133 ; CHECK-NEXT: bb.3.atomicrmw.end:134 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2135 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2136 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)137 ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)138 ; CHECK-NEXT: SI_RETURN implicit $vgpr0139 %oldval = atomicrmw fmin ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst140 ret <2 x half> %oldval141}142 143define <2 x half> @test_atomicrmw_fmax_vector(ptr addrspace(3) %addr) {144 ; CHECK-LABEL: name: test_atomicrmw_fmax_vector145 ; CHECK: bb.1 (%ir-block.0):146 ; CHECK-NEXT: successors: %bb.2(0x80000000)147 ; CHECK-NEXT: liveins: $vgpr0148 ; CHECK-NEXT: {{ $}}149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0150 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00151 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)152 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0153 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)154 ; CHECK-NEXT: G_BR %bb.2155 ; CHECK-NEXT: {{ $}}156 ; CHECK-NEXT: bb.2.atomicrmw.start:157 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %20(s64), %bb.2, [[C1]](s64), %bb.1160 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %19(<2 x s16>), %bb.2161 ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM [[PHI1]], [[BUILD_VECTOR]]162 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FMAXNUM]](<2 x s16>)163 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)164 ; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)165 ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)166 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)167 ; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)168 ; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3169 ; CHECK-NEXT: G_BR %bb.2170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: bb.3.atomicrmw.end:172 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2173 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2174 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)175 ; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)176 ; CHECK-NEXT: SI_RETURN implicit $vgpr0177 %oldval = atomicrmw fmax ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst178 ret <2 x half> %oldval179}180 181