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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -global-isel -global-isel-abort=2 -stop-after=irtranslator -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - %s | FileCheck -enable-var-scope %s3 4declare hidden void @external_void_func_void() #05 6declare hidden void @external_void_func_empty_struct({}, i32) #07declare hidden void @external_void_func_empty_array([0 x i8], i32) #08 9declare hidden void @external_void_func_i1(i1) #010declare hidden void @external_void_func_i1_signext(i1 signext) #011declare hidden void @external_void_func_i1_zeroext(i1 zeroext) #012 13declare hidden void @external_void_func_i8(i8) #014declare hidden void @external_void_func_i8_signext(i8 signext) #015declare hidden void @external_void_func_i8_zeroext(i8 zeroext) #016 17declare hidden void @external_void_func_i16(i16) #018declare hidden void @external_void_func_i16_signext(i16 signext) #019declare hidden void @external_void_func_i16_zeroext(i16 zeroext) #020 21declare hidden void @external_void_func_i32(i32) #022declare hidden void @external_void_func_i64(i64) #023declare hidden void @external_void_func_v2i64(<2 x i64>) #024declare hidden void @external_void_func_v3i64(<3 x i64>) #025declare hidden void @external_void_func_v4i64(<4 x i64>) #026 27 28declare hidden void @external_void_func_i48(i48) #029declare hidden void @external_void_func_i48_signext(i48 signext) #030declare hidden void @external_void_func_i48_zeroext(i48 zeroext) #031 32declare hidden void @external_void_func_p0(ptr) #033declare hidden void @external_void_func_v2p0(<2 x ptr>) #034 35declare hidden void @external_void_func_f16(half) #036declare hidden void @external_void_func_f32(float) #037declare hidden void @external_void_func_f64(double) #038declare hidden void @external_void_func_v2f32(<2 x float>) #039declare hidden void @external_void_func_v2f64(<2 x double>) #040declare hidden void @external_void_func_v3f32(<3 x float>) #041declare hidden void @external_void_func_v3f64(<3 x double>) #042declare hidden void @external_void_func_v5f32(<5 x float>) #043 44declare hidden void @external_void_func_v2i16(<2 x i16>) #045declare hidden void @external_void_func_v2f16(<2 x half>) #046declare hidden void @external_void_func_v3i16(<3 x i16>) #047declare hidden void @external_void_func_v3f16(<3 x half>) #048declare hidden void @external_void_func_v4i16(<4 x i16>) #049declare hidden void @external_void_func_v4f16(<4 x half>) #050declare hidden void @external_void_func_v5i16(<5 x i16>) #051declare hidden void @external_void_func_v7i16(<7 x i16>) #052declare hidden void @external_void_func_v63i16(<63 x i16>) #053declare hidden void @external_void_func_v65i16(<65 x i16>) #054declare hidden void @external_void_func_v66i16(<66 x i16>) #055 56declare hidden void @external_void_func_v2i32(<2 x i32>) #057declare hidden void @external_void_func_v3i32(<3 x i32>) #058declare hidden void @external_void_func_v3i32_i32(<3 x i32>, i32) #059declare hidden void @external_void_func_v4i32(<4 x i32>) #060declare hidden void @external_void_func_v5i32(<5 x i32>) #061declare hidden void @external_void_func_v8i32(<8 x i32>) #062declare hidden void @external_void_func_v16i32(<16 x i32>) #063declare hidden void @external_void_func_v32i32(<32 x i32>) #064declare hidden void @external_void_func_v32i32_i32(<32 x i32>, i32) #065declare hidden void @external_void_func_v32i32_p3_p5(<32 x i32>, ptr addrspace(3), ptr addrspace(5)) #066declare hidden void @external_void_func_v32i32_i8_i8_i16(<32 x i32>, i8, i8, i16) #067 68; Structs69declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #070declare hidden void @external_void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 })) #071declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(ptr addrspace(5) sret({ i8, i32 }), ptr addrspace(5) byval({ i8, i32 })) #072 73declare hidden void @external_void_func_v2i8(<2 x i8>) #074declare hidden void @external_void_func_v3i8(<3 x i8>) #075declare hidden void @external_void_func_v4i8(<4 x i8>) #076declare hidden void @external_void_func_v8i8(<8 x i8>) #077declare hidden void @external_void_func_v16i8(<16 x i8>) #078 79declare hidden void @byval_align16_f64_arg(<32 x i32>, ptr addrspace(5) byval(double) align 16) #080declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #081declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>,82 <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #083declare hidden void @external_void_func_8xv5i32(<5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>,84 <5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>) #085declare hidden void @external_void_func_12xv3f32(<3 x float>, <3 x float>, <3 x float>, <3 x float>,86 <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>) #087declare hidden void @external_void_func_8xv5f32(<5 x float>, <5 x float>, <5 x float>, <5 x float>,88 <5 x float>, <5 x float>, <5 x float>, <5 x float>) #089 90declare hidden void @external_void_func_i16_inreg(i32 inreg) #091declare hidden void @external_void_func_i32_inreg(i32 inreg) #092declare hidden void @external_void_func_i64_inreg(i64 inreg) #093declare hidden void @external_void_func_v2i32_inreg(<2 x i32> inreg) #094declare hidden void @external_void_func_f16_inreg(half inreg) #095declare hidden void @external_void_func_bf16_inreg(bfloat inreg) #096declare hidden void @external_void_func_f32_inreg(float inreg) #097declare hidden void @external_void_func_f64_inreg(double inreg) #098declare hidden void @external_void_func_v2f16_inreg(<2 x half> inreg) #099declare hidden void @external_void_func_v3f16_inreg(<3 x half> inreg) #0100declare hidden void @external_void_func_v4f16_inreg(<4 x half> inreg) #0101 102declare hidden void @external_void_func_p0_inreg(ptr inreg) #0103declare hidden void @external_void_func_p1_inreg(ptr addrspace(1) inreg) #0104declare hidden void @external_void_func_p3_inreg(ptr addrspace(3) inreg) #0105declare hidden void @external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inreg) #0106declare hidden void @external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inreg) #0107 108; amdgpu_gfx calling convention109declare hidden amdgpu_gfx void @external_gfx_void_func_void() #0110declare hidden amdgpu_gfx void @external_gfx_void_func_i32(i32) #0111declare hidden amdgpu_gfx void @external_gfx_void_func_i32_inreg(i32 inreg) #0112declare hidden amdgpu_gfx void @external_gfx_void_func_struct_i8_i32({ i8, i32 }) #0113declare hidden amdgpu_gfx void @external_gfx_void_func_struct_i8_i32_inreg({ i8, i32 } inreg) #0114 115define amdgpu_kernel void @test_call_external_void_func_void() #0 {116 ; CHECK-LABEL: name: test_call_external_void_func_void117 ; CHECK: bb.1 (%ir-block.0):118 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2121 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1122 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0123 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16124 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15125 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14126 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11127 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7128 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5129 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9130 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc131 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_void132 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]133 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]134 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)135 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0136 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)137 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]138 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]139 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]140 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]141 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF142 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)143 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)144 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10145 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)146 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]147 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)148 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20149 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)150 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]151 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg152 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)153 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)154 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)155 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)156 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)157 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)158 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)159 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)160 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)161 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)162 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31163 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc164 ; CHECK-NEXT: S_ENDPGM 0165 call void @external_void_func_void()166 ret void167}168 169define amdgpu_gfx void @test_gfx_call_external_void_func_void() #0 {170 ; CHECK-LABEL: name: test_gfx_call_external_void_func_void171 ; CHECK: bb.1 (%ir-block.0):172 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc173 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_void174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3175 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)176 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_void, csr_amdgpu_si_gfx, implicit $sgpr0_sgpr1_sgpr2_sgpr3177 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc178 ; CHECK-NEXT: SI_RETURN179 call amdgpu_gfx void @external_gfx_void_func_void()180 ret void181}182 183define void @test_func_call_external_void_func_void() #0 {184 ; CHECK-LABEL: name: test_func_call_external_void_func_void185 ; CHECK: bb.1 (%ir-block.0):186 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11187 ; CHECK-NEXT: {{ $}}188 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31189 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr15190 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr14191 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr13192 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr12193 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11194 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9195 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7196 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5197 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc198 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_void199 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]200 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]201 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]202 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY5]]203 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]204 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]205 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]206 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]207 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)208 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3209 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)210 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)211 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)212 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)213 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)214 ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)215 ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)216 ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)217 ; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)218 ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)219 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_void, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31220 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc221 ; CHECK-NEXT: SI_RETURN222 call void @external_void_func_void()223 ret void224}225 226define amdgpu_kernel void @test_call_external_void_func_empty_struct() #0 {227 ; CHECK-LABEL: name: test_call_external_void_func_empty_struct228 ; CHECK: bb.1 (%ir-block.0):229 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11230 ; CHECK-NEXT: {{ $}}231 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2232 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1233 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0234 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16235 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15236 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14237 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11238 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7239 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5240 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9241 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23242 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc243 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_empty_struct244 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]245 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]246 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)247 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0248 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)249 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]250 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]251 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]252 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]253 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF254 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)255 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)256 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10257 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)258 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]259 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)260 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20261 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)262 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]263 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)264 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg265 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)266 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)267 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)268 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)269 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)270 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)271 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)272 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)273 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)274 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)275 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_empty_struct, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31276 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc277 ; CHECK-NEXT: S_ENDPGM 0278 call void @external_void_func_empty_struct({} zeroinitializer, i32 23)279 ret void280}281 282define amdgpu_kernel void @test_call_external_void_func_empty_array() #0 {283 ; CHECK-LABEL: name: test_call_external_void_func_empty_array284 ; CHECK: bb.1 (%ir-block.0):285 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11286 ; CHECK-NEXT: {{ $}}287 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2288 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1289 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0290 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16291 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15292 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14293 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11294 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7295 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5296 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9297 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23298 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc299 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_empty_array300 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]301 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]302 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)303 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0304 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)305 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]306 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]307 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]308 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]309 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF310 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)311 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)312 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10313 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)314 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]315 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)316 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20317 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)318 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]319 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)320 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg321 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)322 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)323 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)324 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)325 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)326 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)327 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)328 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)329 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)330 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)331 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_empty_array, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31332 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc333 ; CHECK-NEXT: S_ENDPGM 0334 call void @external_void_func_empty_array([0 x i8] zeroinitializer, i32 23)335 ret void336}337 338define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {339 ; CHECK-LABEL: name: test_call_external_void_func_i1_imm340 ; CHECK: bb.1 (%ir-block.0):341 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11342 ; CHECK-NEXT: {{ $}}343 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2344 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1345 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0346 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16347 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15348 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14349 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11350 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7351 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5352 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9353 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true354 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc355 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i1356 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]357 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]358 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)359 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0360 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)361 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]362 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]363 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]364 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]365 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF366 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)367 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)368 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10369 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)370 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]371 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)372 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20373 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)374 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]375 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s1)376 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)377 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg378 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)379 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)380 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)381 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)382 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)383 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)384 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)385 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)386 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)387 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)388 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i1, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31389 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc390 ; CHECK-NEXT: S_ENDPGM 0391 call void @external_void_func_i1(i1 true)392 ret void393}394 395define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {396 ; CHECK-LABEL: name: test_call_external_void_func_i1_signext397 ; CHECK: bb.1 (%ir-block.1):398 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11399 ; CHECK-NEXT: {{ $}}400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2401 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1402 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0403 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16404 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15405 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14406 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11407 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7408 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5409 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9410 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF411 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)412 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s1) from `ptr addrspace(1) poison`, addrspace 1)413 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc414 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i1_signext415 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]416 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]417 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)418 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4419 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)420 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]421 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]422 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]423 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]424 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF425 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)426 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)427 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10428 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)429 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]430 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)431 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20432 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)433 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]434 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s1)435 ; CHECK-NEXT: $vgpr0 = COPY [[SEXT]](s32)436 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg437 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)438 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)439 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)440 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)441 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)442 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)443 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)444 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)445 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)446 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)447 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i1_signext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31448 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc449 ; CHECK-NEXT: S_ENDPGM 0450 %var = load volatile i1, ptr addrspace(1) poison451 call void @external_void_func_i1_signext(i1 signext %var)452 ret void453}454 455define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {456 ; CHECK-LABEL: name: test_call_external_void_func_i1_zeroext457 ; CHECK: bb.1 (%ir-block.1):458 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11459 ; CHECK-NEXT: {{ $}}460 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2461 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1462 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0463 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16464 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15465 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14466 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11467 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7468 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5469 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9470 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF471 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)472 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s1) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s1) from `ptr addrspace(1) poison`, addrspace 1)473 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc474 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i1_zeroext475 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]476 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]477 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)478 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4479 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)480 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]481 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]482 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]483 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]484 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF485 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)486 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)487 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10488 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)489 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]490 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)491 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20492 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)493 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]494 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s1)495 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](s32)496 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg497 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)498 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)499 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)500 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)501 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)502 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)503 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)504 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)505 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)506 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)507 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i1_zeroext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31508 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc509 ; CHECK-NEXT: S_ENDPGM 0510 %var = load volatile i1, ptr addrspace(1) poison511 call void @external_void_func_i1_zeroext(i1 zeroext %var)512 ret void513}514 515define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {516 ; CHECK-LABEL: name: test_call_external_void_func_i8_imm517 ; CHECK: bb.1 (%ir-block.1):518 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11519 ; CHECK-NEXT: {{ $}}520 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2521 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1522 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0523 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16524 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15525 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14526 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11527 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7528 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5529 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9530 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 123531 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)532 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc533 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i8534 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]535 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]536 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)537 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4538 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)539 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]540 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]541 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]542 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]543 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF544 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)545 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)546 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10547 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)548 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]549 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)550 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20551 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)552 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]553 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[C]](s8)554 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)555 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)556 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg557 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)558 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)559 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)560 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)561 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)562 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)563 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)564 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)565 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)566 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)567 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i8, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31568 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc569 ; CHECK-NEXT: S_ENDPGM 0570 call void @external_void_func_i8(i8 123)571 ret void572}573 574define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {575 ; CHECK-LABEL: name: test_call_external_void_func_i8_signext576 ; CHECK: bb.1 (%ir-block.1):577 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11578 ; CHECK-NEXT: {{ $}}579 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2580 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1581 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0582 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16583 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15584 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14585 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11586 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7587 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5588 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9589 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF590 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)591 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s8) from `ptr addrspace(1) poison`, addrspace 1)592 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc593 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i8_signext594 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]595 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]596 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)597 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4598 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)599 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]600 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]601 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]602 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]603 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF604 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)605 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)606 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10607 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)608 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]609 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)610 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20611 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)612 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]613 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[LOAD]](s8)614 ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[SEXT]](s16)615 ; CHECK-NEXT: $vgpr0 = COPY [[SEXT1]](s32)616 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg617 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)618 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)619 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)620 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)621 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)622 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)623 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)624 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)625 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)626 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)627 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i8_signext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31628 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc629 ; CHECK-NEXT: S_ENDPGM 0630 %var = load volatile i8, ptr addrspace(1) poison631 call void @external_void_func_i8_signext(i8 signext %var)632 ret void633}634 635define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {636 ; CHECK-LABEL: name: test_call_external_void_func_i8_zeroext637 ; CHECK: bb.1 (%ir-block.1):638 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11639 ; CHECK-NEXT: {{ $}}640 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2641 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1642 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0643 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16644 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15645 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14646 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11647 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7648 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5649 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9650 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF651 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)652 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s8) from `ptr addrspace(1) poison`, addrspace 1)653 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc654 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i8_zeroext655 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]656 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]657 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)658 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4659 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)660 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]661 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]662 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]663 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]664 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF665 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)666 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)667 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10668 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)669 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]670 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)671 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20672 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)673 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]674 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[LOAD]](s8)675 ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ZEXT]](s16)676 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT1]](s32)677 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg678 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)679 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)680 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)681 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)682 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)683 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)684 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)685 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)686 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)687 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)688 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i8_zeroext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31689 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc690 ; CHECK-NEXT: S_ENDPGM 0691 %var = load volatile i8, ptr addrspace(1) poison692 call void @external_void_func_i8_zeroext(i8 zeroext %var)693 ret void694}695 696define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {697 ; CHECK-LABEL: name: test_call_external_void_func_i16_imm698 ; CHECK: bb.1 (%ir-block.0):699 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11700 ; CHECK-NEXT: {{ $}}701 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2702 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1703 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0704 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16705 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15706 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14707 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11708 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7709 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5710 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9711 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 123712 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc713 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i16714 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]715 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]716 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)717 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0718 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)719 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]720 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]721 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]722 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]723 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF724 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)725 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)726 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10727 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)728 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]729 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)730 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20731 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)732 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]733 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)734 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)735 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg736 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)737 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)738 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)739 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)740 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)741 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)742 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)743 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)744 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)745 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)746 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31747 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc748 ; CHECK-NEXT: S_ENDPGM 0749 call void @external_void_func_i16(i16 123)750 ret void751}752 753define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {754 ; CHECK-LABEL: name: test_call_external_void_func_i16_signext755 ; CHECK: bb.1 (%ir-block.1):756 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11757 ; CHECK-NEXT: {{ $}}758 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2759 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1760 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0761 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16762 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15763 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14764 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11765 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7766 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5767 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9768 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF769 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)770 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s16) from `ptr addrspace(1) poison`, addrspace 1)771 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc772 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i16_signext773 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]774 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]775 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)776 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4777 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)778 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]779 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]780 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]781 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]782 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF783 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)784 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)785 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10786 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)787 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]788 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)789 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20790 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)791 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]792 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[LOAD]](s16)793 ; CHECK-NEXT: $vgpr0 = COPY [[SEXT]](s32)794 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg795 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)796 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)797 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)798 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)799 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)800 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)801 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)802 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)803 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)804 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)805 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16_signext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31806 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc807 ; CHECK-NEXT: S_ENDPGM 0808 %var = load volatile i16, ptr addrspace(1) poison809 call void @external_void_func_i16_signext(i16 signext %var)810 ret void811}812 813define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {814 ; CHECK-LABEL: name: test_call_external_void_func_i16_zeroext815 ; CHECK: bb.1 (%ir-block.1):816 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11817 ; CHECK-NEXT: {{ $}}818 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2819 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1820 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0821 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16822 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15823 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14824 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11825 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7826 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5827 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9828 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF829 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)830 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s16) from `ptr addrspace(1) poison`, addrspace 1)831 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc832 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i16_zeroext833 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]834 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]835 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)836 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4837 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)838 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]839 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]840 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]841 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]842 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF843 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)844 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)845 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 10846 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)847 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]848 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)849 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 20850 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)851 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]852 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)853 ; CHECK-NEXT: $vgpr0 = COPY [[ZEXT]](s32)854 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg855 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)856 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)857 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)858 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)859 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)860 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)861 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)862 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)863 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)864 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)865 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16_zeroext, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31866 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc867 ; CHECK-NEXT: S_ENDPGM 0868 %var = load volatile i16, ptr addrspace(1) poison869 call void @external_void_func_i16_zeroext(i16 zeroext %var)870 ret void871}872 873define amdgpu_kernel void @test_call_external_void_func_i32_imm(i32) #0 {874 ; CHECK-LABEL: name: test_call_external_void_func_i32_imm875 ; CHECK: bb.1 (%ir-block.1):876 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11877 ; CHECK-NEXT: {{ $}}878 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2879 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1880 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0881 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16882 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15883 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14884 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11885 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7886 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5887 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9888 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42889 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)890 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc891 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i32892 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]893 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]894 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)895 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4896 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)897 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]898 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]899 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]900 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]901 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF902 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)903 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)904 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 10905 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)906 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]907 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)908 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 20909 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)910 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]911 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)912 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg913 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)914 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)915 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)916 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)917 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)918 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)919 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)920 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)921 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)922 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)923 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31924 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc925 ; CHECK-NEXT: S_ENDPGM 0926 call void @external_void_func_i32(i32 42)927 ret void928}929 930define amdgpu_gfx void @test_gfx_call_external_void_func_i32_imm(i32) #0 {931 ; CHECK-LABEL: name: test_gfx_call_external_void_func_i32_imm932 ; CHECK: bb.1 (%ir-block.1):933 ; CHECK-NEXT: liveins: $vgpr0934 ; CHECK-NEXT: {{ $}}935 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0936 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42937 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc938 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_i32939 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)940 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3941 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)942 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_i32, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3943 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc944 ; CHECK-NEXT: SI_RETURN945 call amdgpu_gfx void @external_gfx_void_func_i32(i32 42)946 ret void947}948 949define amdgpu_gfx void @test_gfx_call_external_void_func_i32_imm_inreg(i32 inreg) #0 {950 ; CHECK-LABEL: name: test_gfx_call_external_void_func_i32_imm_inreg951 ; CHECK: bb.1 (%ir-block.1):952 ; CHECK-NEXT: liveins: $sgpr4953 ; CHECK-NEXT: {{ $}}954 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr4955 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42956 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc957 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_i32_inreg958 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[C]](s32)959 ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32)960 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3961 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>)962 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3963 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc964 ; CHECK-NEXT: SI_RETURN965 call amdgpu_gfx void @external_gfx_void_func_i32_inreg(i32 inreg 42)966 ret void967}968 969define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {970 ; CHECK-LABEL: name: test_call_external_void_func_i64_imm971 ; CHECK: bb.1 (%ir-block.0):972 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11973 ; CHECK-NEXT: {{ $}}974 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2975 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1976 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0977 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16978 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15979 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14980 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11981 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7982 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5983 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9984 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 123985 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc986 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i64987 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]988 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]989 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)990 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0991 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)992 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]993 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]994 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]995 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]996 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF997 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)998 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)999 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 101000 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)1001 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1002 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1003 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 201004 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)1005 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1006 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)1007 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1008 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1009 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1010 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1011 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1012 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1013 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1014 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1015 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1016 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1017 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1018 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1019 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1020 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311021 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1022 ; CHECK-NEXT: S_ENDPGM 01023 call void @external_void_func_i64(i64 123)1024 ret void1025}1026 1027define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {1028 ; CHECK-LABEL: name: test_call_external_void_func_v2i641029 ; CHECK: bb.1 (%ir-block.0):1030 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111031 ; CHECK-NEXT: {{ $}}1032 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21033 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11034 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01035 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161036 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151037 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141038 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111039 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71040 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51041 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91042 ; CHECK-NEXT: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 01043 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: ("amdgpu-noclobber" load (<2 x s64>) from `ptr addrspace(1) null`, addrspace 1)1044 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1045 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i641046 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1047 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1048 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1049 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01050 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)1051 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1052 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1053 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1054 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1055 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1056 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1057 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1058 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 101059 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)1060 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1061 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1062 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 201063 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)1064 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1065 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s64>)1066 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1067 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1068 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1069 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)1070 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1071 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1072 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1073 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1074 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1075 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1076 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1077 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1078 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1079 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1080 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1081 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311082 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1083 ; CHECK-NEXT: S_ENDPGM 01084 %val = load <2 x i64>, ptr addrspace(1) null1085 call void @external_void_func_v2i64(<2 x i64> %val)1086 ret void1087}1088 1089define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {1090 ; CHECK-LABEL: name: test_call_external_void_func_v2i64_imm1091 ; CHECK: bb.1 (%ir-block.0):1092 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111093 ; CHECK-NEXT: {{ $}}1094 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21095 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11096 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01097 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161098 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151099 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141100 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111101 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71102 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51103 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91104 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 85899345931105 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 171798691871106 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)1107 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1108 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i641109 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1110 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1111 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1112 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 01113 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C2]](s64)1114 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1115 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1116 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1117 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1118 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1119 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1120 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1121 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 101122 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)1123 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1124 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1125 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 201126 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)1127 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1128 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s64>)1129 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1130 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1131 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1132 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)1133 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1134 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1135 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1136 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1137 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1138 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1139 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1140 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1141 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1142 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1143 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1144 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311145 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1146 ; CHECK-NEXT: S_ENDPGM 01147 call void @external_void_func_v2i64(<2 x i64> <i64 8589934593, i64 17179869187>)1148 ret void1149}1150 1151define amdgpu_kernel void @test_call_external_void_func_i48(i32) #0 {1152 ; CHECK-LABEL: name: test_call_external_void_func_i481153 ; CHECK: bb.1 (%ir-block.1):1154 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111155 ; CHECK-NEXT: {{ $}}1156 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21157 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11158 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01159 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161160 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151161 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141162 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111163 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71164 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51165 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91166 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF1167 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)1168 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s48) from `ptr addrspace(1) poison`, align 8, addrspace 1)1169 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1170 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i481171 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1172 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1173 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1174 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 41175 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)1176 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1177 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1178 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1179 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1180 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1181 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1182 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1183 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 101184 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)1185 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1186 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1187 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 201188 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)1189 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1190 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s48)1191 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ANYEXT]](s64)1192 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1193 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1194 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1195 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1196 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1197 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1198 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1199 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1200 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1201 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1202 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1203 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)1204 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1205 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i48, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311206 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1207 ; CHECK-NEXT: S_ENDPGM 01208 %var = load volatile i48, ptr addrspace(1) poison1209 call void @external_void_func_i48(i48 %var)1210 ret void1211}1212 1213define amdgpu_kernel void @test_call_external_void_func_i48_signext(i32) #0 {1214 ; CHECK-LABEL: name: test_call_external_void_func_i48_signext1215 ; CHECK: bb.1 (%ir-block.1):1216 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111217 ; CHECK-NEXT: {{ $}}1218 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21219 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11220 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01221 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161222 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151223 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141224 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111225 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71226 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51227 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91228 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF1229 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)1230 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s48) from `ptr addrspace(1) poison`, align 8, addrspace 1)1231 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1232 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i48_signext1233 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1234 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1235 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1236 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 41237 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)1238 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1239 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1240 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1241 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1242 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1243 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1244 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1245 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 101246 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)1247 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1248 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1249 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 201250 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)1251 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1252 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s48)1253 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT]](s64)1254 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1255 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1256 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1257 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1258 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1259 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1260 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1261 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1262 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1263 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1264 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1265 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)1266 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1267 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i48_signext, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311268 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1269 ; CHECK-NEXT: S_ENDPGM 01270 %var = load volatile i48, ptr addrspace(1) poison1271 call void @external_void_func_i48_signext(i48 signext %var)1272 ret void1273}1274 1275define amdgpu_kernel void @test_call_external_void_func_i48_zeroext(i32) #0 {1276 ; CHECK-LABEL: name: test_call_external_void_func_i48_zeroext1277 ; CHECK: bb.1 (%ir-block.1):1278 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111279 ; CHECK-NEXT: {{ $}}1280 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21281 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11282 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01283 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161284 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151285 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141286 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111287 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71288 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51289 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91290 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF1291 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)1292 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s48) = G_LOAD [[DEF]](p1) :: (volatile "amdgpu-noclobber" load (s48) from `ptr addrspace(1) poison`, align 8, addrspace 1)1293 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1294 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i48_zeroext1295 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1296 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1297 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1298 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 41299 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)1300 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1301 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1302 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1303 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1304 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1305 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1306 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1307 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 101308 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)1309 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1310 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1311 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 201312 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)1313 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1314 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s48)1315 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64)1316 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1317 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1318 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1319 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1320 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1321 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1322 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1323 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1324 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1325 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1326 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1327 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)1328 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1329 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i48_zeroext, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311330 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1331 ; CHECK-NEXT: S_ENDPGM 01332 %var = load volatile i48, ptr addrspace(1) poison1333 call void @external_void_func_i48_zeroext(i48 zeroext %var)1334 ret void1335}1336 1337define amdgpu_kernel void @test_call_external_void_func_p0_imm(ptr %arg) #0 {1338 ; CHECK-LABEL: name: test_call_external_void_func_p0_imm1339 ; CHECK: bb.1 (%ir-block.0):1340 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111341 ; CHECK-NEXT: {{ $}}1342 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21343 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11344 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01345 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161346 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151347 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141348 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111349 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71350 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51351 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91352 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)1353 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load (p0) from %ir.arg.kernarg.offset1, align 16, addrspace 4)1354 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1355 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_p01356 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1357 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1358 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1359 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81360 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)1361 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1362 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1363 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1364 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1365 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1366 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1367 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1368 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 101369 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)1370 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1371 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1372 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 201373 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)1374 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1375 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p0)1376 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1377 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1378 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1379 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1380 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1381 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1382 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1383 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1384 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1385 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1386 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1387 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1388 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1389 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311390 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1391 ; CHECK-NEXT: S_ENDPGM 01392 call void @external_void_func_p0(ptr %arg)1393 ret void1394}1395 1396define amdgpu_kernel void @test_call_external_void_func_v2p0() #0 {1397 ; CHECK-LABEL: name: test_call_external_void_func_v2p01398 ; CHECK: bb.1 (%ir-block.0):1399 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111400 ; CHECK-NEXT: {{ $}}1401 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21402 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11403 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01404 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161405 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151406 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141407 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111408 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71409 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51410 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91411 ; CHECK-NEXT: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 01412 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x p0>) = G_LOAD [[C]](p1) :: ("amdgpu-noclobber" load (<2 x p0>) from `ptr addrspace(1) null`, addrspace 1)1413 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1414 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2p01415 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1416 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1417 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1418 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01419 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)1420 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1421 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1422 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1423 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1424 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1425 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1426 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1427 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 101428 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)1429 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1430 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1431 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 201432 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)1433 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1434 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x p0>)1435 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1436 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1437 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1438 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)1439 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1440 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1441 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1442 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1443 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1444 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1445 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1446 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1447 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1448 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1449 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1450 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2p0, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311451 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1452 ; CHECK-NEXT: S_ENDPGM 01453 %val = load <2 x ptr>, ptr addrspace(1) null1454 call void @external_void_func_v2p0(<2 x ptr> %val)1455 ret void1456}1457 1458define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {1459 ; CHECK-LABEL: name: test_call_external_void_func_v3i641460 ; CHECK: bb.1 (%ir-block.0):1461 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111462 ; CHECK-NEXT: {{ $}}1463 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21464 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11465 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01466 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161467 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151468 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141469 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111470 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71471 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51472 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91473 ; CHECK-NEXT: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 01474 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 85899345931475 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF1476 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[DEF]](s64)1477 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: ("amdgpu-noclobber" load (<2 x s64>) from `ptr addrspace(1) null`, addrspace 1)1478 ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<3 x s64>) = G_SHUFFLE_VECTOR [[LOAD]](<2 x s64>), [[BUILD_VECTOR]], shufflemask(0, 1, 2)1479 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1480 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3i641481 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1482 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1483 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1484 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 01485 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C2]](s64)1486 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1487 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1488 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1489 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1490 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1491 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1492 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1493 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 101494 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)1495 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1496 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1497 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 201498 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)1499 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1500 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SHUF]](<3 x s64>)1501 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1502 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1503 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1504 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)1505 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)1506 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)1507 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1508 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1509 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1510 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1511 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1512 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1513 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1514 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1515 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1516 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)1517 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1518 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311519 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1520 ; CHECK-NEXT: S_ENDPGM 01521 %load = load <2 x i64>, ptr addrspace(1) null1522 %val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 poison>, <3 x i32> <i32 0, i32 1, i32 2>1523 1524 call void @external_void_func_v3i64(<3 x i64> %val)1525 ret void1526}1527 1528define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {1529 ; CHECK-LABEL: name: test_call_external_void_func_v4i641530 ; CHECK: bb.1 (%ir-block.0):1531 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111532 ; CHECK-NEXT: {{ $}}1533 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21534 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11535 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01536 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161537 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151538 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141539 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111540 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71541 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51542 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91543 ; CHECK-NEXT: [[C:%[0-9]+]]:_(p1) = G_CONSTANT i64 01544 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 85899345931545 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 171798691871546 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C2]](s64)1547 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[C]](p1) :: ("amdgpu-noclobber" load (<2 x s64>) from `ptr addrspace(1) null`, addrspace 1)1548 ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s64>) = G_SHUFFLE_VECTOR [[LOAD]](<2 x s64>), [[BUILD_VECTOR]], shufflemask(0, 1, 2, 3)1549 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1550 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4i641551 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1552 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1553 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1554 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 01555 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C3]](s64)1556 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1557 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1558 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1559 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1560 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1561 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1562 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1563 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 101564 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)1565 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1566 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1567 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 201568 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)1569 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1570 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SHUF]](<4 x s64>)1571 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1572 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1573 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1574 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)1575 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)1576 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)1577 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)1578 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)1579 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1580 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1581 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1582 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1583 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1584 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1585 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1586 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1587 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1588 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1589 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1590 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311591 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1592 ; CHECK-NEXT: S_ENDPGM 01593 %load = load <2 x i64>, ptr addrspace(1) null1594 %val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 17179869187>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1595 call void @external_void_func_v4i64(<4 x i64> %val)1596 ret void1597}1598 1599define amdgpu_kernel void @test_call_external_void_func_f16_imm() #0 {1600 ; CHECK-LABEL: name: test_call_external_void_func_f16_imm1601 ; CHECK: bb.1 (%ir-block.0):1602 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111603 ; CHECK-NEXT: {{ $}}1604 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21605 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11606 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01607 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161608 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151609 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141610 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111611 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71612 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51613 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91614 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH44001615 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1616 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f161617 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1618 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1619 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1620 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01621 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)1622 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1623 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1624 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1625 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1626 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1627 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1628 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1629 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 101630 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)1631 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1632 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1633 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 201634 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)1635 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1636 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)1637 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)1638 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1639 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1640 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1641 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1642 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1643 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1644 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1645 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1646 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1647 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1648 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1649 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311650 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1651 ; CHECK-NEXT: S_ENDPGM 01652 call void @external_void_func_f16(half 4.0)1653 ret void1654}1655 1656define amdgpu_kernel void @test_call_external_void_func_f32_imm() #0 {1657 ; CHECK-LABEL: name: test_call_external_void_func_f32_imm1658 ; CHECK: bb.1 (%ir-block.0):1659 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111660 ; CHECK-NEXT: {{ $}}1661 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21662 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11663 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01664 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161665 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151666 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141667 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111668 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71669 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51670 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91671 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+001672 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1673 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f321674 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1675 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1676 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1677 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01678 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)1679 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1680 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1681 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1682 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1683 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1684 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1685 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1686 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 101687 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)1688 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1689 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1690 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 201691 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)1692 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1693 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)1694 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1695 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1696 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1697 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1698 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1699 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1700 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1701 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1702 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1703 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1704 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1705 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311706 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1707 ; CHECK-NEXT: S_ENDPGM 01708 call void @external_void_func_f32(float 4.0)1709 ret void1710}1711 1712define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {1713 ; CHECK-LABEL: name: test_call_external_void_func_v2f32_imm1714 ; CHECK: bb.1 (%ir-block.0):1715 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111716 ; CHECK-NEXT: {{ $}}1717 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21718 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11719 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01720 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161721 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151722 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141723 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111724 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71725 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51726 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91727 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+001728 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+001729 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)1730 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1731 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2f321732 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1733 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1734 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1735 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 01736 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C2]](s64)1737 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1738 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1739 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1740 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1741 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1742 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1743 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1744 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 101745 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)1746 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1747 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1748 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 201749 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)1750 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1751 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)1752 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1753 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1754 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1755 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1756 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1757 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1758 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1759 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1760 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1761 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1762 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1763 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1764 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1765 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311766 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1767 ; CHECK-NEXT: S_ENDPGM 01768 call void @external_void_func_v2f32(<2 x float> <float 1.0, float 2.0>)1769 ret void1770}1771 1772define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {1773 ; CHECK-LABEL: name: test_call_external_void_func_v3f32_imm1774 ; CHECK: bb.1 (%ir-block.0):1775 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111776 ; CHECK-NEXT: {{ $}}1777 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21778 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11779 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01780 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161781 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151782 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141783 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111784 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71785 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51786 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91787 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+001788 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+001789 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+001790 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)1791 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1792 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3f321793 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1794 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1795 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1796 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 01797 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C3]](s64)1798 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1799 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1800 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1801 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1802 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1803 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1804 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1805 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 101806 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)1807 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1808 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1809 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 201810 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)1811 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1812 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)1813 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1814 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1815 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1816 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1817 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1818 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1819 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1820 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1821 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1822 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1823 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1824 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1825 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1826 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1827 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311828 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1829 ; CHECK-NEXT: S_ENDPGM 01830 call void @external_void_func_v3f32(<3 x float> <float 1.0, float 2.0, float 4.0>)1831 ret void1832}1833 1834define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {1835 ; CHECK-LABEL: name: test_call_external_void_func_v5f32_imm1836 ; CHECK: bb.1 (%ir-block.0):1837 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111838 ; CHECK-NEXT: {{ $}}1839 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21840 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11841 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01842 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161843 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151844 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141845 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111846 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71847 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51848 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91849 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+001850 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+001851 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+001852 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float -1.000000e+001853 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e-011854 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)1855 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1856 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v5f321857 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1858 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1859 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1860 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 01861 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C5]](s64)1862 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1863 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1864 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1865 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1866 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1867 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1868 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1869 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 101870 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)1871 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1872 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1873 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 201874 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)1875 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1876 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)1877 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1878 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1879 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)1880 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)1881 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)1882 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1883 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1884 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1885 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1886 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1887 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1888 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1889 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1890 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1891 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1892 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1893 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v5f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311894 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1895 ; CHECK-NEXT: S_ENDPGM 01896 call void @external_void_func_v5f32(<5 x float> <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>)1897 ret void1898}1899 1900define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {1901 ; CHECK-LABEL: name: test_call_external_void_func_f64_imm1902 ; CHECK: bb.1 (%ir-block.0):1903 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111904 ; CHECK-NEXT: {{ $}}1905 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21906 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11907 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01908 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161909 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151910 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141911 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111912 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71913 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51914 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91915 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+001916 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1917 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f641918 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1919 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1920 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1921 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01922 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)1923 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1924 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1925 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1926 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1927 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1928 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1929 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1930 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 101931 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)1932 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1933 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1934 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 201935 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)1936 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1937 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)1938 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1939 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)1940 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg1941 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)1942 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)1943 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)1944 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)1945 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)1946 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)1947 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)1948 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)1949 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)1950 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)1951 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr311952 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc1953 ; CHECK-NEXT: S_ENDPGM 01954 call void @external_void_func_f64(double 4.0)1955 ret void1956}1957 1958define amdgpu_kernel void @test_call_external_void_func_v2f64_imm() #0 {1959 ; CHECK-LABEL: name: test_call_external_void_func_v2f64_imm1960 ; CHECK: bb.1 (%ir-block.0):1961 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr111962 ; CHECK-NEXT: {{ $}}1963 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr21964 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr11965 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr01966 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr161967 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr151968 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr141969 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr111970 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr71971 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr51972 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr91973 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001974 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+001975 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64)1976 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc1977 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2f641978 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]1979 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]1980 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)1981 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 01982 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C2]](s64)1983 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]1984 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]1985 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]1986 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]1987 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF1988 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)1989 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)1990 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 101991 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)1992 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]1993 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)1994 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 201995 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)1996 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]1997 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s64>)1998 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)1999 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)2000 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)2001 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)2002 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2003 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2004 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2005 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2006 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2007 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2008 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2009 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2010 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2011 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)2012 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2013 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312014 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2015 ; CHECK-NEXT: S_ENDPGM 02016 call void @external_void_func_v2f64(<2 x double> <double 2.0, double 4.0>)2017 ret void2018}2019 2020define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {2021 ; CHECK-LABEL: name: test_call_external_void_func_v3f64_imm2022 ; CHECK: bb.1 (%ir-block.0):2023 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112024 ; CHECK-NEXT: {{ $}}2025 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22026 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12027 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02028 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162029 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152030 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142031 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112032 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72033 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52034 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92035 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+002036 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+002037 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+002038 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C1]](s64), [[C2]](s64)2039 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2040 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3f642041 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2042 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2043 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2044 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 02045 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C3]](s64)2046 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2047 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2048 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2049 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2050 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2051 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2052 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2053 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 102054 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)2055 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2056 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2057 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 202058 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)2059 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2060 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s64>)2061 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)2062 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)2063 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)2064 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)2065 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)2066 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)2067 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2068 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2069 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2070 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2071 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2072 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2073 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2074 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2075 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2076 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)2077 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2078 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f64, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312079 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2080 ; CHECK-NEXT: S_ENDPGM 02081 call void @external_void_func_v3f64(<3 x double> <double 2.0, double 4.0, double 8.0>)2082 ret void2083}2084 2085define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {2086 ; CHECK-LABEL: name: test_call_external_void_func_v2i162087 ; CHECK: bb.1 (%ir-block.0):2088 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112089 ; CHECK-NEXT: {{ $}}2090 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22091 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12092 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02093 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162094 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152095 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142096 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112097 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72098 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52099 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92100 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2101 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<2 x s16>) from `ptr addrspace(1) poison`, addrspace 1)2102 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2103 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i162104 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2105 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2106 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2107 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02108 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2109 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2110 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2111 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2112 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2113 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2114 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2115 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2116 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102117 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2118 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2119 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2120 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202121 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2122 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2123 ; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)2124 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2125 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2126 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2127 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2128 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2129 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2130 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2131 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2132 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2133 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2134 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2135 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312136 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2137 ; CHECK-NEXT: S_ENDPGM 02138 %val = load <2 x i16>, ptr addrspace(1) poison2139 call void @external_void_func_v2i16(<2 x i16> %val)2140 ret void2141}2142 2143define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {2144 ; CHECK-LABEL: name: test_call_external_void_func_v3i162145 ; CHECK: bb.1 (%ir-block.0):2146 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112147 ; CHECK-NEXT: {{ $}}2148 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22149 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12150 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02151 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162152 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152153 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142154 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112155 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72156 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52157 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92158 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2159 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<3 x s16>) from `ptr addrspace(1) poison`, align 8, addrspace 1)2160 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2161 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3i162162 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2163 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2164 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2165 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02166 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2167 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2168 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2169 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2170 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2171 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2172 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2173 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2174 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102175 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2176 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2177 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2178 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202179 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2180 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2181 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<3 x s16>)2182 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF2183 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[DEF2]](s16)2184 ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)2185 ; CHECK-NEXT: $vgpr0 = COPY [[UV3]](<2 x s16>)2186 ; CHECK-NEXT: $vgpr1 = COPY [[UV4]](<2 x s16>)2187 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2188 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2189 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2190 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2191 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2192 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2193 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2194 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2195 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2196 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2197 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2198 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312199 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2200 ; CHECK-NEXT: S_ENDPGM 02201 %val = load <3 x i16>, ptr addrspace(1) poison2202 call void @external_void_func_v3i16(<3 x i16> %val)2203 ret void2204}2205 2206define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {2207 ; CHECK-LABEL: name: test_call_external_void_func_v3f162208 ; CHECK: bb.1 (%ir-block.0):2209 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112210 ; CHECK-NEXT: {{ $}}2211 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22212 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12213 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02214 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162215 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152216 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142217 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112218 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72219 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52220 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92221 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2222 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<3 x s16>) from `ptr addrspace(1) poison`, align 8, addrspace 1)2223 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2224 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3f162225 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2226 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2227 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2228 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02229 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2230 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2231 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2232 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2233 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2234 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2235 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2236 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2237 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102238 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2239 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2240 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2241 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202242 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2243 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2244 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<3 x s16>)2245 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF2246 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[DEF2]](s16)2247 ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)2248 ; CHECK-NEXT: $vgpr0 = COPY [[UV3]](<2 x s16>)2249 ; CHECK-NEXT: $vgpr1 = COPY [[UV4]](<2 x s16>)2250 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2251 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2252 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2253 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2254 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2255 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2256 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2257 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2258 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2259 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2260 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2261 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312262 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2263 ; CHECK-NEXT: S_ENDPGM 02264 %val = load <3 x half>, ptr addrspace(1) poison2265 call void @external_void_func_v3f16(<3 x half> %val)2266 ret void2267}2268 2269define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {2270 ; CHECK-LABEL: name: test_call_external_void_func_v4i162271 ; CHECK: bb.1 (%ir-block.0):2272 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112273 ; CHECK-NEXT: {{ $}}2274 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22275 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12276 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02277 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162278 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152279 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142280 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112281 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72282 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52283 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92284 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2285 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<4 x s16>) from `ptr addrspace(1) poison`, addrspace 1)2286 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2287 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4i162288 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2289 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2290 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2291 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02292 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2293 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2294 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2295 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2296 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2297 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2298 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2299 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2300 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102301 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2302 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2303 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2304 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202305 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2306 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2307 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[LOAD]](<4 x s16>)2308 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)2309 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)2310 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2311 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2312 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2313 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2314 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2315 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2316 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2317 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2318 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2319 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2320 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2321 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312322 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2323 ; CHECK-NEXT: S_ENDPGM 02324 %val = load <4 x i16>, ptr addrspace(1) poison2325 call void @external_void_func_v4i16(<4 x i16> %val)2326 ret void2327}2328 2329define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {2330 ; CHECK-LABEL: name: test_call_external_void_func_v4i16_imm2331 ; CHECK: bb.1 (%ir-block.0):2332 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112333 ; CHECK-NEXT: {{ $}}2334 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22335 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12336 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02337 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162338 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152339 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142340 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112341 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72342 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52343 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92344 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 12345 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 22346 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 32347 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 42348 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16), [[C2]](s16), [[C3]](s16)2349 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2350 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4i162351 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2352 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2353 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2354 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 02355 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C4]](s64)2356 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2357 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2358 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2359 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2360 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2361 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2362 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2363 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 102364 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)2365 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2366 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2367 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 202368 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)2369 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2370 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s16>)2371 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)2372 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)2373 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2374 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2375 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2376 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2377 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2378 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2379 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2380 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2381 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2382 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)2383 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2384 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312385 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2386 ; CHECK-NEXT: S_ENDPGM 02387 call void @external_void_func_v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>)2388 ret void2389}2390 2391define amdgpu_kernel void @test_call_external_void_func_v5i16() #0 {2392 ; CHECK-LABEL: name: test_call_external_void_func_v5i162393 ; CHECK: bb.1 (%ir-block.0):2394 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112395 ; CHECK-NEXT: {{ $}}2396 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22397 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12398 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02399 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162400 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152401 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142402 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112403 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72404 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52405 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92406 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2407 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<5 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<5 x s16>) from `ptr addrspace(1) poison`, align 16, addrspace 1)2408 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2409 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v5i162410 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2411 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2412 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2413 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02414 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2415 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2416 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2417 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2418 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2419 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2420 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2421 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2422 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102423 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2424 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2425 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2426 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202427 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2428 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2429 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<5 x s16>)2430 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF2431 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<6 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[DEF2]](s16)2432 ; CHECK-NEXT: [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<6 x s16>)2433 ; CHECK-NEXT: $vgpr0 = COPY [[UV5]](<2 x s16>)2434 ; CHECK-NEXT: $vgpr1 = COPY [[UV6]](<2 x s16>)2435 ; CHECK-NEXT: $vgpr2 = COPY [[UV7]](<2 x s16>)2436 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2437 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2438 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2439 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2440 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2441 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2442 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2443 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2444 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2445 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2446 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2447 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v5i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312448 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2449 ; CHECK-NEXT: S_ENDPGM 02450 %val = load <5 x i16>, ptr addrspace(1) poison2451 call void @external_void_func_v5i16(<5 x i16> %val)2452 ret void2453}2454 2455define amdgpu_kernel void @test_call_external_void_func_v7i16() #0 {2456 ; CHECK-LABEL: name: test_call_external_void_func_v7i162457 ; CHECK: bb.1 (%ir-block.0):2458 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112459 ; CHECK-NEXT: {{ $}}2460 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22461 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12462 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02463 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162464 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152465 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142466 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112467 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72468 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52469 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92470 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2471 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<7 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<7 x s16>) from `ptr addrspace(1) poison`, align 16, addrspace 1)2472 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2473 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v7i162474 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2475 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2476 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2477 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02478 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2479 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2480 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2481 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2482 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2483 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2484 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2485 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2486 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102487 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2488 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2489 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2490 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202491 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2492 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2493 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<7 x s16>)2494 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF2495 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[DEF2]](s16)2496 ; CHECK-NEXT: [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s16>)2497 ; CHECK-NEXT: $vgpr0 = COPY [[UV7]](<2 x s16>)2498 ; CHECK-NEXT: $vgpr1 = COPY [[UV8]](<2 x s16>)2499 ; CHECK-NEXT: $vgpr2 = COPY [[UV9]](<2 x s16>)2500 ; CHECK-NEXT: $vgpr3 = COPY [[UV10]](<2 x s16>)2501 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2502 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2503 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2504 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2505 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2506 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2507 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2508 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2509 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2510 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2511 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2512 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v7i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312513 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2514 ; CHECK-NEXT: S_ENDPGM 02515 %val = load <7 x i16>, ptr addrspace(1) poison2516 call void @external_void_func_v7i16(<7 x i16> %val)2517 ret void2518}2519 2520define amdgpu_kernel void @test_call_external_void_func_v63i16() #0 {2521 ; CHECK-LABEL: name: test_call_external_void_func_v63i162522 ; CHECK: bb.1 (%ir-block.0):2523 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112524 ; CHECK-NEXT: {{ $}}2525 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22526 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12527 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02528 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162529 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152530 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142531 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112532 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72533 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52534 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92535 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2536 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<63 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<63 x s16>) from `ptr addrspace(1) poison`, align 128, addrspace 1)2537 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2538 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v63i162539 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2540 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2541 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2542 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02543 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2544 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2545 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2546 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2547 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2548 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2549 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2550 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2551 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102552 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2553 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2554 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2555 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202556 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2557 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2558 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16), [[UV15:%[0-9]+]]:_(s16), [[UV16:%[0-9]+]]:_(s16), [[UV17:%[0-9]+]]:_(s16), [[UV18:%[0-9]+]]:_(s16), [[UV19:%[0-9]+]]:_(s16), [[UV20:%[0-9]+]]:_(s16), [[UV21:%[0-9]+]]:_(s16), [[UV22:%[0-9]+]]:_(s16), [[UV23:%[0-9]+]]:_(s16), [[UV24:%[0-9]+]]:_(s16), [[UV25:%[0-9]+]]:_(s16), [[UV26:%[0-9]+]]:_(s16), [[UV27:%[0-9]+]]:_(s16), [[UV28:%[0-9]+]]:_(s16), [[UV29:%[0-9]+]]:_(s16), [[UV30:%[0-9]+]]:_(s16), [[UV31:%[0-9]+]]:_(s16), [[UV32:%[0-9]+]]:_(s16), [[UV33:%[0-9]+]]:_(s16), [[UV34:%[0-9]+]]:_(s16), [[UV35:%[0-9]+]]:_(s16), [[UV36:%[0-9]+]]:_(s16), [[UV37:%[0-9]+]]:_(s16), [[UV38:%[0-9]+]]:_(s16), [[UV39:%[0-9]+]]:_(s16), [[UV40:%[0-9]+]]:_(s16), [[UV41:%[0-9]+]]:_(s16), [[UV42:%[0-9]+]]:_(s16), [[UV43:%[0-9]+]]:_(s16), [[UV44:%[0-9]+]]:_(s16), [[UV45:%[0-9]+]]:_(s16), [[UV46:%[0-9]+]]:_(s16), [[UV47:%[0-9]+]]:_(s16), [[UV48:%[0-9]+]]:_(s16), [[UV49:%[0-9]+]]:_(s16), [[UV50:%[0-9]+]]:_(s16), [[UV51:%[0-9]+]]:_(s16), [[UV52:%[0-9]+]]:_(s16), [[UV53:%[0-9]+]]:_(s16), [[UV54:%[0-9]+]]:_(s16), [[UV55:%[0-9]+]]:_(s16), [[UV56:%[0-9]+]]:_(s16), [[UV57:%[0-9]+]]:_(s16), [[UV58:%[0-9]+]]:_(s16), [[UV59:%[0-9]+]]:_(s16), [[UV60:%[0-9]+]]:_(s16), [[UV61:%[0-9]+]]:_(s16), [[UV62:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<63 x s16>)2559 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF2560 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<64 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[UV7]](s16), [[UV8]](s16), [[UV9]](s16), [[UV10]](s16), [[UV11]](s16), [[UV12]](s16), [[UV13]](s16), [[UV14]](s16), [[UV15]](s16), [[UV16]](s16), [[UV17]](s16), [[UV18]](s16), [[UV19]](s16), [[UV20]](s16), [[UV21]](s16), [[UV22]](s16), [[UV23]](s16), [[UV24]](s16), [[UV25]](s16), [[UV26]](s16), [[UV27]](s16), [[UV28]](s16), [[UV29]](s16), [[UV30]](s16), [[UV31]](s16), [[UV32]](s16), [[UV33]](s16), [[UV34]](s16), [[UV35]](s16), [[UV36]](s16), [[UV37]](s16), [[UV38]](s16), [[UV39]](s16), [[UV40]](s16), [[UV41]](s16), [[UV42]](s16), [[UV43]](s16), [[UV44]](s16), [[UV45]](s16), [[UV46]](s16), [[UV47]](s16), [[UV48]](s16), [[UV49]](s16), [[UV50]](s16), [[UV51]](s16), [[UV52]](s16), [[UV53]](s16), [[UV54]](s16), [[UV55]](s16), [[UV56]](s16), [[UV57]](s16), [[UV58]](s16), [[UV59]](s16), [[UV60]](s16), [[UV61]](s16), [[UV62]](s16), [[DEF2]](s16)2561 ; CHECK-NEXT: [[UV63:%[0-9]+]]:_(<2 x s16>), [[UV64:%[0-9]+]]:_(<2 x s16>), [[UV65:%[0-9]+]]:_(<2 x s16>), [[UV66:%[0-9]+]]:_(<2 x s16>), [[UV67:%[0-9]+]]:_(<2 x s16>), [[UV68:%[0-9]+]]:_(<2 x s16>), [[UV69:%[0-9]+]]:_(<2 x s16>), [[UV70:%[0-9]+]]:_(<2 x s16>), [[UV71:%[0-9]+]]:_(<2 x s16>), [[UV72:%[0-9]+]]:_(<2 x s16>), [[UV73:%[0-9]+]]:_(<2 x s16>), [[UV74:%[0-9]+]]:_(<2 x s16>), [[UV75:%[0-9]+]]:_(<2 x s16>), [[UV76:%[0-9]+]]:_(<2 x s16>), [[UV77:%[0-9]+]]:_(<2 x s16>), [[UV78:%[0-9]+]]:_(<2 x s16>), [[UV79:%[0-9]+]]:_(<2 x s16>), [[UV80:%[0-9]+]]:_(<2 x s16>), [[UV81:%[0-9]+]]:_(<2 x s16>), [[UV82:%[0-9]+]]:_(<2 x s16>), [[UV83:%[0-9]+]]:_(<2 x s16>), [[UV84:%[0-9]+]]:_(<2 x s16>), [[UV85:%[0-9]+]]:_(<2 x s16>), [[UV86:%[0-9]+]]:_(<2 x s16>), [[UV87:%[0-9]+]]:_(<2 x s16>), [[UV88:%[0-9]+]]:_(<2 x s16>), [[UV89:%[0-9]+]]:_(<2 x s16>), [[UV90:%[0-9]+]]:_(<2 x s16>), [[UV91:%[0-9]+]]:_(<2 x s16>), [[UV92:%[0-9]+]]:_(<2 x s16>), [[UV93:%[0-9]+]]:_(<2 x s16>), [[UV94:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<64 x s16>)2562 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg2563 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 02564 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)2565 ; CHECK-NEXT: G_STORE [[UV94]](<2 x s16>), [[PTR_ADD1]](p5) :: (store (<2 x s16>) into stack, align 16, addrspace 5)2566 ; CHECK-NEXT: $vgpr0 = COPY [[UV63]](<2 x s16>)2567 ; CHECK-NEXT: $vgpr1 = COPY [[UV64]](<2 x s16>)2568 ; CHECK-NEXT: $vgpr2 = COPY [[UV65]](<2 x s16>)2569 ; CHECK-NEXT: $vgpr3 = COPY [[UV66]](<2 x s16>)2570 ; CHECK-NEXT: $vgpr4 = COPY [[UV67]](<2 x s16>)2571 ; CHECK-NEXT: $vgpr5 = COPY [[UV68]](<2 x s16>)2572 ; CHECK-NEXT: $vgpr6 = COPY [[UV69]](<2 x s16>)2573 ; CHECK-NEXT: $vgpr7 = COPY [[UV70]](<2 x s16>)2574 ; CHECK-NEXT: $vgpr8 = COPY [[UV71]](<2 x s16>)2575 ; CHECK-NEXT: $vgpr9 = COPY [[UV72]](<2 x s16>)2576 ; CHECK-NEXT: $vgpr10 = COPY [[UV73]](<2 x s16>)2577 ; CHECK-NEXT: $vgpr11 = COPY [[UV74]](<2 x s16>)2578 ; CHECK-NEXT: $vgpr12 = COPY [[UV75]](<2 x s16>)2579 ; CHECK-NEXT: $vgpr13 = COPY [[UV76]](<2 x s16>)2580 ; CHECK-NEXT: $vgpr14 = COPY [[UV77]](<2 x s16>)2581 ; CHECK-NEXT: $vgpr15 = COPY [[UV78]](<2 x s16>)2582 ; CHECK-NEXT: $vgpr16 = COPY [[UV79]](<2 x s16>)2583 ; CHECK-NEXT: $vgpr17 = COPY [[UV80]](<2 x s16>)2584 ; CHECK-NEXT: $vgpr18 = COPY [[UV81]](<2 x s16>)2585 ; CHECK-NEXT: $vgpr19 = COPY [[UV82]](<2 x s16>)2586 ; CHECK-NEXT: $vgpr20 = COPY [[UV83]](<2 x s16>)2587 ; CHECK-NEXT: $vgpr21 = COPY [[UV84]](<2 x s16>)2588 ; CHECK-NEXT: $vgpr22 = COPY [[UV85]](<2 x s16>)2589 ; CHECK-NEXT: $vgpr23 = COPY [[UV86]](<2 x s16>)2590 ; CHECK-NEXT: $vgpr24 = COPY [[UV87]](<2 x s16>)2591 ; CHECK-NEXT: $vgpr25 = COPY [[UV88]](<2 x s16>)2592 ; CHECK-NEXT: $vgpr26 = COPY [[UV89]](<2 x s16>)2593 ; CHECK-NEXT: $vgpr27 = COPY [[UV90]](<2 x s16>)2594 ; CHECK-NEXT: $vgpr28 = COPY [[UV91]](<2 x s16>)2595 ; CHECK-NEXT: $vgpr29 = COPY [[UV92]](<2 x s16>)2596 ; CHECK-NEXT: $vgpr30 = COPY [[UV93]](<2 x s16>)2597 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2598 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2599 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2600 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2601 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2602 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2603 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2604 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2605 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2606 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2607 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2608 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v63i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312609 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc2610 ; CHECK-NEXT: S_ENDPGM 02611 %val = load <63 x i16>, ptr addrspace(1) poison2612 call void @external_void_func_v63i16(<63 x i16> %val)2613 ret void2614}2615 2616define amdgpu_kernel void @test_call_external_void_func_v65i16() #0 {2617 ; CHECK-LABEL: name: test_call_external_void_func_v65i162618 ; CHECK: bb.1 (%ir-block.0):2619 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112620 ; CHECK-NEXT: {{ $}}2621 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22622 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12623 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02624 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162625 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152626 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142627 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112628 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72629 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52630 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92631 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2632 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<65 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<65 x s16>) from `ptr addrspace(1) poison`, align 256, addrspace 1)2633 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2634 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v65i162635 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2636 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2637 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2638 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02639 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2640 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2641 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2642 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2643 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2644 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2645 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2646 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2647 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102648 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2649 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2650 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2651 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202652 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2653 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2654 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16), [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16), [[UV15:%[0-9]+]]:_(s16), [[UV16:%[0-9]+]]:_(s16), [[UV17:%[0-9]+]]:_(s16), [[UV18:%[0-9]+]]:_(s16), [[UV19:%[0-9]+]]:_(s16), [[UV20:%[0-9]+]]:_(s16), [[UV21:%[0-9]+]]:_(s16), [[UV22:%[0-9]+]]:_(s16), [[UV23:%[0-9]+]]:_(s16), [[UV24:%[0-9]+]]:_(s16), [[UV25:%[0-9]+]]:_(s16), [[UV26:%[0-9]+]]:_(s16), [[UV27:%[0-9]+]]:_(s16), [[UV28:%[0-9]+]]:_(s16), [[UV29:%[0-9]+]]:_(s16), [[UV30:%[0-9]+]]:_(s16), [[UV31:%[0-9]+]]:_(s16), [[UV32:%[0-9]+]]:_(s16), [[UV33:%[0-9]+]]:_(s16), [[UV34:%[0-9]+]]:_(s16), [[UV35:%[0-9]+]]:_(s16), [[UV36:%[0-9]+]]:_(s16), [[UV37:%[0-9]+]]:_(s16), [[UV38:%[0-9]+]]:_(s16), [[UV39:%[0-9]+]]:_(s16), [[UV40:%[0-9]+]]:_(s16), [[UV41:%[0-9]+]]:_(s16), [[UV42:%[0-9]+]]:_(s16), [[UV43:%[0-9]+]]:_(s16), [[UV44:%[0-9]+]]:_(s16), [[UV45:%[0-9]+]]:_(s16), [[UV46:%[0-9]+]]:_(s16), [[UV47:%[0-9]+]]:_(s16), [[UV48:%[0-9]+]]:_(s16), [[UV49:%[0-9]+]]:_(s16), [[UV50:%[0-9]+]]:_(s16), [[UV51:%[0-9]+]]:_(s16), [[UV52:%[0-9]+]]:_(s16), [[UV53:%[0-9]+]]:_(s16), [[UV54:%[0-9]+]]:_(s16), [[UV55:%[0-9]+]]:_(s16), [[UV56:%[0-9]+]]:_(s16), [[UV57:%[0-9]+]]:_(s16), [[UV58:%[0-9]+]]:_(s16), [[UV59:%[0-9]+]]:_(s16), [[UV60:%[0-9]+]]:_(s16), [[UV61:%[0-9]+]]:_(s16), [[UV62:%[0-9]+]]:_(s16), [[UV63:%[0-9]+]]:_(s16), [[UV64:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<65 x s16>)2655 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF2656 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<66 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16), [[UV3]](s16), [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[UV7]](s16), [[UV8]](s16), [[UV9]](s16), [[UV10]](s16), [[UV11]](s16), [[UV12]](s16), [[UV13]](s16), [[UV14]](s16), [[UV15]](s16), [[UV16]](s16), [[UV17]](s16), [[UV18]](s16), [[UV19]](s16), [[UV20]](s16), [[UV21]](s16), [[UV22]](s16), [[UV23]](s16), [[UV24]](s16), [[UV25]](s16), [[UV26]](s16), [[UV27]](s16), [[UV28]](s16), [[UV29]](s16), [[UV30]](s16), [[UV31]](s16), [[UV32]](s16), [[UV33]](s16), [[UV34]](s16), [[UV35]](s16), [[UV36]](s16), [[UV37]](s16), [[UV38]](s16), [[UV39]](s16), [[UV40]](s16), [[UV41]](s16), [[UV42]](s16), [[UV43]](s16), [[UV44]](s16), [[UV45]](s16), [[UV46]](s16), [[UV47]](s16), [[UV48]](s16), [[UV49]](s16), [[UV50]](s16), [[UV51]](s16), [[UV52]](s16), [[UV53]](s16), [[UV54]](s16), [[UV55]](s16), [[UV56]](s16), [[UV57]](s16), [[UV58]](s16), [[UV59]](s16), [[UV60]](s16), [[UV61]](s16), [[UV62]](s16), [[UV63]](s16), [[UV64]](s16), [[DEF2]](s16)2657 ; CHECK-NEXT: [[UV65:%[0-9]+]]:_(<2 x s16>), [[UV66:%[0-9]+]]:_(<2 x s16>), [[UV67:%[0-9]+]]:_(<2 x s16>), [[UV68:%[0-9]+]]:_(<2 x s16>), [[UV69:%[0-9]+]]:_(<2 x s16>), [[UV70:%[0-9]+]]:_(<2 x s16>), [[UV71:%[0-9]+]]:_(<2 x s16>), [[UV72:%[0-9]+]]:_(<2 x s16>), [[UV73:%[0-9]+]]:_(<2 x s16>), [[UV74:%[0-9]+]]:_(<2 x s16>), [[UV75:%[0-9]+]]:_(<2 x s16>), [[UV76:%[0-9]+]]:_(<2 x s16>), [[UV77:%[0-9]+]]:_(<2 x s16>), [[UV78:%[0-9]+]]:_(<2 x s16>), [[UV79:%[0-9]+]]:_(<2 x s16>), [[UV80:%[0-9]+]]:_(<2 x s16>), [[UV81:%[0-9]+]]:_(<2 x s16>), [[UV82:%[0-9]+]]:_(<2 x s16>), [[UV83:%[0-9]+]]:_(<2 x s16>), [[UV84:%[0-9]+]]:_(<2 x s16>), [[UV85:%[0-9]+]]:_(<2 x s16>), [[UV86:%[0-9]+]]:_(<2 x s16>), [[UV87:%[0-9]+]]:_(<2 x s16>), [[UV88:%[0-9]+]]:_(<2 x s16>), [[UV89:%[0-9]+]]:_(<2 x s16>), [[UV90:%[0-9]+]]:_(<2 x s16>), [[UV91:%[0-9]+]]:_(<2 x s16>), [[UV92:%[0-9]+]]:_(<2 x s16>), [[UV93:%[0-9]+]]:_(<2 x s16>), [[UV94:%[0-9]+]]:_(<2 x s16>), [[UV95:%[0-9]+]]:_(<2 x s16>), [[UV96:%[0-9]+]]:_(<2 x s16>), [[UV97:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<66 x s16>)2658 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg2659 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 02660 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)2661 ; CHECK-NEXT: G_STORE [[UV96]](<2 x s16>), [[PTR_ADD1]](p5) :: (store (<2 x s16>) into stack, align 16, addrspace 5)2662 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 42663 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)2664 ; CHECK-NEXT: G_STORE [[UV97]](<2 x s16>), [[PTR_ADD2]](p5) :: (store (<2 x s16>) into stack + 4, addrspace 5)2665 ; CHECK-NEXT: $vgpr0 = COPY [[UV65]](<2 x s16>)2666 ; CHECK-NEXT: $vgpr1 = COPY [[UV66]](<2 x s16>)2667 ; CHECK-NEXT: $vgpr2 = COPY [[UV67]](<2 x s16>)2668 ; CHECK-NEXT: $vgpr3 = COPY [[UV68]](<2 x s16>)2669 ; CHECK-NEXT: $vgpr4 = COPY [[UV69]](<2 x s16>)2670 ; CHECK-NEXT: $vgpr5 = COPY [[UV70]](<2 x s16>)2671 ; CHECK-NEXT: $vgpr6 = COPY [[UV71]](<2 x s16>)2672 ; CHECK-NEXT: $vgpr7 = COPY [[UV72]](<2 x s16>)2673 ; CHECK-NEXT: $vgpr8 = COPY [[UV73]](<2 x s16>)2674 ; CHECK-NEXT: $vgpr9 = COPY [[UV74]](<2 x s16>)2675 ; CHECK-NEXT: $vgpr10 = COPY [[UV75]](<2 x s16>)2676 ; CHECK-NEXT: $vgpr11 = COPY [[UV76]](<2 x s16>)2677 ; CHECK-NEXT: $vgpr12 = COPY [[UV77]](<2 x s16>)2678 ; CHECK-NEXT: $vgpr13 = COPY [[UV78]](<2 x s16>)2679 ; CHECK-NEXT: $vgpr14 = COPY [[UV79]](<2 x s16>)2680 ; CHECK-NEXT: $vgpr15 = COPY [[UV80]](<2 x s16>)2681 ; CHECK-NEXT: $vgpr16 = COPY [[UV81]](<2 x s16>)2682 ; CHECK-NEXT: $vgpr17 = COPY [[UV82]](<2 x s16>)2683 ; CHECK-NEXT: $vgpr18 = COPY [[UV83]](<2 x s16>)2684 ; CHECK-NEXT: $vgpr19 = COPY [[UV84]](<2 x s16>)2685 ; CHECK-NEXT: $vgpr20 = COPY [[UV85]](<2 x s16>)2686 ; CHECK-NEXT: $vgpr21 = COPY [[UV86]](<2 x s16>)2687 ; CHECK-NEXT: $vgpr22 = COPY [[UV87]](<2 x s16>)2688 ; CHECK-NEXT: $vgpr23 = COPY [[UV88]](<2 x s16>)2689 ; CHECK-NEXT: $vgpr24 = COPY [[UV89]](<2 x s16>)2690 ; CHECK-NEXT: $vgpr25 = COPY [[UV90]](<2 x s16>)2691 ; CHECK-NEXT: $vgpr26 = COPY [[UV91]](<2 x s16>)2692 ; CHECK-NEXT: $vgpr27 = COPY [[UV92]](<2 x s16>)2693 ; CHECK-NEXT: $vgpr28 = COPY [[UV93]](<2 x s16>)2694 ; CHECK-NEXT: $vgpr29 = COPY [[UV94]](<2 x s16>)2695 ; CHECK-NEXT: $vgpr30 = COPY [[UV95]](<2 x s16>)2696 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2697 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2698 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2699 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2700 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2701 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2702 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2703 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2704 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2705 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2706 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2707 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v65i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312708 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc2709 ; CHECK-NEXT: S_ENDPGM 02710 %val = load <65 x i16>, ptr addrspace(1) poison2711 call void @external_void_func_v65i16(<65 x i16> %val)2712 ret void2713}2714 2715define amdgpu_kernel void @test_call_external_void_func_v66i16() #0 {2716 ; CHECK-LABEL: name: test_call_external_void_func_v66i162717 ; CHECK: bb.1 (%ir-block.0):2718 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112719 ; CHECK-NEXT: {{ $}}2720 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22721 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12722 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02723 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162724 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152725 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142726 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112727 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72728 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52729 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92730 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2731 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<66 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<66 x s16>) from `ptr addrspace(1) poison`, align 256, addrspace 1)2732 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2733 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v66i162734 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2735 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2736 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2737 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02738 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2739 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2740 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2741 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2742 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2743 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2744 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2745 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2746 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102747 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2748 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2749 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2750 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202751 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2752 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2753 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>), [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>), [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>), [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>), [[UV24:%[0-9]+]]:_(<2 x s16>), [[UV25:%[0-9]+]]:_(<2 x s16>), [[UV26:%[0-9]+]]:_(<2 x s16>), [[UV27:%[0-9]+]]:_(<2 x s16>), [[UV28:%[0-9]+]]:_(<2 x s16>), [[UV29:%[0-9]+]]:_(<2 x s16>), [[UV30:%[0-9]+]]:_(<2 x s16>), [[UV31:%[0-9]+]]:_(<2 x s16>), [[UV32:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[LOAD]](<66 x s16>)2754 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg2755 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 02756 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)2757 ; CHECK-NEXT: G_STORE [[UV31]](<2 x s16>), [[PTR_ADD1]](p5) :: (store (<2 x s16>) into stack, align 16, addrspace 5)2758 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 42759 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)2760 ; CHECK-NEXT: G_STORE [[UV32]](<2 x s16>), [[PTR_ADD2]](p5) :: (store (<2 x s16>) into stack + 4, addrspace 5)2761 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](<2 x s16>)2762 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](<2 x s16>)2763 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](<2 x s16>)2764 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](<2 x s16>)2765 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](<2 x s16>)2766 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](<2 x s16>)2767 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](<2 x s16>)2768 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](<2 x s16>)2769 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](<2 x s16>)2770 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](<2 x s16>)2771 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](<2 x s16>)2772 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](<2 x s16>)2773 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](<2 x s16>)2774 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](<2 x s16>)2775 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](<2 x s16>)2776 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](<2 x s16>)2777 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](<2 x s16>)2778 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](<2 x s16>)2779 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](<2 x s16>)2780 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](<2 x s16>)2781 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](<2 x s16>)2782 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](<2 x s16>)2783 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](<2 x s16>)2784 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](<2 x s16>)2785 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](<2 x s16>)2786 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](<2 x s16>)2787 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](<2 x s16>)2788 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](<2 x s16>)2789 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](<2 x s16>)2790 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](<2 x s16>)2791 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](<2 x s16>)2792 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2793 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2794 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2795 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2796 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2797 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2798 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2799 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2800 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2801 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2802 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2803 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v66i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312804 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc2805 ; CHECK-NEXT: S_ENDPGM 02806 %val = load <66 x i16>, ptr addrspace(1) poison2807 call void @external_void_func_v66i16(<66 x i16> %val)2808 ret void2809}2810 2811define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {2812 ; CHECK-LABEL: name: test_call_external_void_func_v2f162813 ; CHECK: bb.1 (%ir-block.0):2814 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112815 ; CHECK-NEXT: {{ $}}2816 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22817 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12818 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02819 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162820 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152821 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142822 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112823 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72824 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52825 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92826 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2827 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<2 x s16>) from `ptr addrspace(1) poison`, addrspace 1)2828 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2829 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2f162830 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2831 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2832 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2833 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02834 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2835 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2836 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2837 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2838 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2839 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2840 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2841 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2842 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102843 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2844 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2845 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2846 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202847 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2848 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2849 ; CHECK-NEXT: $vgpr0 = COPY [[LOAD]](<2 x s16>)2850 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2851 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2852 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2853 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2854 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2855 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2856 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2857 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2858 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2859 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2860 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2861 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f16, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312862 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2863 ; CHECK-NEXT: S_ENDPGM 02864 %val = load <2 x half>, ptr addrspace(1) poison2865 call void @external_void_func_v2f16(<2 x half> %val)2866 ret void2867}2868 2869define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {2870 ; CHECK-LABEL: name: test_call_external_void_func_v2i322871 ; CHECK: bb.1 (%ir-block.0):2872 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112873 ; CHECK-NEXT: {{ $}}2874 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22875 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12876 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02877 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162878 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152879 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142880 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112881 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72882 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52883 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92884 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF2885 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s32>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<2 x s32>) from `ptr addrspace(1) poison`, addrspace 1)2886 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2887 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i322888 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2889 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2890 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2891 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 02892 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)2893 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2894 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2895 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2896 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2897 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2898 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2899 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2900 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 102901 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)2902 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2903 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2904 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 202905 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)2906 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2907 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)2908 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)2909 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)2910 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2911 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2912 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2913 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2914 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2915 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2916 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2917 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2918 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2919 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)2920 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2921 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312922 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2923 ; CHECK-NEXT: S_ENDPGM 02924 %val = load <2 x i32>, ptr addrspace(1) poison2925 call void @external_void_func_v2i32(<2 x i32> %val)2926 ret void2927}2928 2929define amdgpu_kernel void @test_call_external_void_func_v2i32_imm() #0 {2930 ; CHECK-LABEL: name: test_call_external_void_func_v2i32_imm2931 ; CHECK: bb.1 (%ir-block.0):2932 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112933 ; CHECK-NEXT: {{ $}}2934 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22935 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12936 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02937 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162938 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152939 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr142940 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr112941 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr72942 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr52943 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr92944 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 12945 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 22946 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32)2947 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc2948 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i322949 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]2950 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]2951 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)2952 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 02953 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C2]](s64)2954 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]2955 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]2956 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]2957 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]2958 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF2959 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)2960 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)2961 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 102962 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C3]](s32)2963 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]2964 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)2965 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 202966 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)2967 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]2968 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)2969 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)2970 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)2971 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg2972 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)2973 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)2974 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)2975 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)2976 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)2977 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)2978 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)2979 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)2980 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)2981 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)2982 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr312983 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc2984 ; CHECK-NEXT: S_ENDPGM 02985 call void @external_void_func_v2i32(<2 x i32> <i32 1, i32 2>)2986 ret void2987}2988 2989define amdgpu_kernel void @test_call_external_void_func_v3i32_imm(i32) #0 {2990 ; CHECK-LABEL: name: test_call_external_void_func_v3i32_imm2991 ; CHECK: bb.1 (%ir-block.1):2992 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr112993 ; CHECK-NEXT: {{ $}}2994 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr22995 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr12996 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr02997 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr162998 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr152999 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143000 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113001 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73002 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53003 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93004 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33005 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 43006 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 53007 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)3008 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)3009 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3010 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3i323011 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3012 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3013 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3014 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 43015 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C3]](s64)3016 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3017 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3018 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3019 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3020 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3021 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3022 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3023 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 103024 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)3025 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3026 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3027 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 203028 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)3029 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3030 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)3031 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3032 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3033 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3034 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3035 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3036 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3037 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3038 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3039 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3040 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3041 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3042 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3043 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)3044 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3045 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313046 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3047 ; CHECK-NEXT: S_ENDPGM 03048 call void @external_void_func_v3i32(<3 x i32> <i32 3, i32 4, i32 5>)3049 ret void3050}3051 3052define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {3053 ; CHECK-LABEL: name: test_call_external_void_func_v3i32_i323054 ; CHECK: bb.1 (%ir-block.1):3055 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113056 ; CHECK-NEXT: {{ $}}3057 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23058 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13059 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03060 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163061 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153062 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143063 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113064 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73065 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53066 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93067 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33068 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 43069 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 53070 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32)3071 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 63072 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)3073 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3074 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3i32_i323075 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3076 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3077 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3078 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 43079 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C4]](s64)3080 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3081 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3082 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3083 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3084 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3085 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3086 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3087 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 103088 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)3089 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3090 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3091 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 203092 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)3093 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3094 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)3095 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3096 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3097 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3098 ; CHECK-NEXT: $vgpr3 = COPY [[C3]](s32)3099 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3100 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3101 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3102 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3103 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3104 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3105 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3106 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3107 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3108 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)3109 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3110 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i32_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313111 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3112 ; CHECK-NEXT: S_ENDPGM 03113 call void @external_void_func_v3i32_i32(<3 x i32> <i32 3, i32 4, i32 5>, i32 6)3114 ret void3115}3116 3117define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {3118 ; CHECK-LABEL: name: test_call_external_void_func_v4i323119 ; CHECK: bb.1 (%ir-block.0):3120 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113121 ; CHECK-NEXT: {{ $}}3122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23123 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13124 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03125 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163126 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153127 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143128 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113129 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73130 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53131 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93132 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF3133 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[DEF]](p1) :: ("amdgpu-noclobber" load (<4 x s32>) from `ptr addrspace(1) poison`, addrspace 1)3134 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3135 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4i323136 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3137 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3138 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3139 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 03140 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3141 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3142 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3143 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3144 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3145 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3146 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3147 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3148 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103149 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3150 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3151 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3152 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203153 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3154 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3155 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<4 x s32>)3156 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3157 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3158 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3159 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3160 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3161 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3162 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3163 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3164 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3165 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3166 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3167 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3168 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3169 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)3170 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3171 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313172 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3173 ; CHECK-NEXT: S_ENDPGM 03174 %val = load <4 x i32>, ptr addrspace(1) poison3175 call void @external_void_func_v4i32(<4 x i32> %val)3176 ret void3177}3178 3179define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {3180 ; CHECK-LABEL: name: test_call_external_void_func_v4i32_imm3181 ; CHECK: bb.1 (%ir-block.0):3182 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113183 ; CHECK-NEXT: {{ $}}3184 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23185 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13186 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03187 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163188 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153189 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143190 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113191 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73192 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53193 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93194 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13195 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23196 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 33197 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 43198 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)3199 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3200 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4i323201 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3202 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3203 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3204 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 03205 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C4]](s64)3206 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3207 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3208 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3209 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3210 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3211 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3212 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3213 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 103214 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C5]](s32)3215 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3216 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3217 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 203218 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C6]](s32)3219 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3220 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<4 x s32>)3221 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3222 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3223 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3224 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3225 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3226 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3227 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3228 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3229 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3230 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3231 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3232 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3233 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3234 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)3235 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3236 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313237 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3238 ; CHECK-NEXT: S_ENDPGM 03239 call void @external_void_func_v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>)3240 ret void3241}3242 3243define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {3244 ; CHECK-LABEL: name: test_call_external_void_func_v5i32_imm3245 ; CHECK: bb.1 (%ir-block.0):3246 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113247 ; CHECK-NEXT: {{ $}}3248 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23249 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13250 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03251 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163252 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153253 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143254 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113255 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73256 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53257 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93258 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13259 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23260 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 33261 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 43262 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 53263 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32)3264 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3265 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v5i323266 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3267 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3268 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3269 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 03270 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C5]](s64)3271 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3272 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3273 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3274 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3275 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3276 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3277 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3278 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 103279 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C6]](s32)3280 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3281 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3282 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 203283 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C7]](s32)3284 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3285 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)3286 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3287 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3288 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3289 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3290 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3291 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3292 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3293 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3294 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3295 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3296 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3297 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3298 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3299 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3300 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)3301 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3302 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v5i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313303 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3304 ; CHECK-NEXT: S_ENDPGM 03305 call void @external_void_func_v5i32(<5 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5>)3306 ret void3307}3308 3309define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {3310 ; CHECK-LABEL: name: test_call_external_void_func_v8i323311 ; CHECK: bb.1 (%ir-block.0):3312 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113313 ; CHECK-NEXT: {{ $}}3314 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23315 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13316 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03317 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163318 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153319 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143320 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113321 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73322 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53323 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93324 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3325 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3326 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<8 x s32>) from %ir.ptr, addrspace 1)3327 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3328 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v8i323329 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3330 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3331 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3332 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 03333 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3334 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3335 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3336 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3337 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3338 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3339 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3340 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3341 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103342 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3343 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3344 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3345 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203346 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3347 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3348 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<8 x s32>)3349 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3350 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3351 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3352 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3353 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3354 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3355 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3356 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3357 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3358 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3359 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3360 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3361 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3362 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3363 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3364 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3365 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3366 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)3367 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3368 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v8i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313369 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3370 ; CHECK-NEXT: S_ENDPGM 03371 %ptr = load ptr addrspace(1), ptr addrspace(4) poison3372 %val = load <8 x i32>, ptr addrspace(1) %ptr3373 call void @external_void_func_v8i32(<8 x i32> %val)3374 ret void3375}3376 3377define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {3378 ; CHECK-LABEL: name: test_call_external_void_func_v8i32_imm3379 ; CHECK: bb.1 (%ir-block.0):3380 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113381 ; CHECK-NEXT: {{ $}}3382 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23383 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13384 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03385 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163386 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153387 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143388 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113389 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73390 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53391 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93392 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 13393 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 23394 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 33395 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 43396 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 53397 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 63398 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 73399 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 83400 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32), [[C4]](s32), [[C5]](s32), [[C6]](s32), [[C7]](s32)3401 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3402 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v8i323403 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3404 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3405 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3406 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 03407 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C8]](s64)3408 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3409 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3410 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3411 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3412 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3413 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3414 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3415 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 103416 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C9]](s32)3417 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3418 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3419 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 203420 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C10]](s32)3421 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3422 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<8 x s32>)3423 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3424 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3425 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3426 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3427 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3428 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3429 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3430 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3431 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3432 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3433 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3434 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3435 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3436 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3437 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3438 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3439 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3440 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)3441 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3442 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v8i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313443 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3444 ; CHECK-NEXT: S_ENDPGM 03445 call void @external_void_func_v8i32(<8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>)3446 ret void3447}3448 3449define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {3450 ; CHECK-LABEL: name: test_call_external_void_func_v16i323451 ; CHECK: bb.1 (%ir-block.0):3452 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113453 ; CHECK-NEXT: {{ $}}3454 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23455 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13456 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03457 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163458 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153459 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143460 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113461 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73462 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53463 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93464 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3465 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3466 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x s32>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<16 x s32>) from %ir.ptr, addrspace 1)3467 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3468 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v16i323469 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3470 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3471 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3472 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 03473 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3474 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3475 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3476 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3477 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3478 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3479 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3480 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3481 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103482 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3483 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3484 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3485 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203486 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3487 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3488 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<16 x s32>)3489 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3490 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3491 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3492 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3493 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3494 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3495 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3496 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3497 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)3498 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)3499 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)3500 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)3501 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)3502 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)3503 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)3504 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)3505 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3506 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3507 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3508 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3509 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3510 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3511 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3512 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3513 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3514 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)3515 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3516 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v16i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313517 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc3518 ; CHECK-NEXT: S_ENDPGM 03519 %ptr = load ptr addrspace(1), ptr addrspace(4) poison3520 %val = load <16 x i32>, ptr addrspace(1) %ptr3521 call void @external_void_func_v16i32(<16 x i32> %val)3522 ret void3523}3524 3525define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {3526 ; CHECK-LABEL: name: test_call_external_void_func_v32i323527 ; CHECK: bb.1 (%ir-block.0):3528 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113529 ; CHECK-NEXT: {{ $}}3530 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23531 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13532 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03533 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163534 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153535 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143536 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113537 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73538 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53539 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93540 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3541 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3542 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<32 x s32>) from %ir.ptr, addrspace 1)3543 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3544 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v32i323545 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3546 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3547 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3548 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 03549 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3550 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3551 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3552 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3553 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3554 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3555 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3556 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3557 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103558 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3559 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3560 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3561 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203562 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3563 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3564 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)3565 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg3566 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 03567 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)3568 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack, align 16, addrspace 5)3569 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3570 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3571 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3572 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3573 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3574 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3575 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3576 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3577 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)3578 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)3579 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)3580 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)3581 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)3582 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)3583 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)3584 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)3585 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)3586 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)3587 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)3588 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)3589 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)3590 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)3591 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)3592 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)3593 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)3594 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)3595 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)3596 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)3597 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)3598 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)3599 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)3600 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3601 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3602 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3603 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3604 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3605 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3606 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3607 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3608 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3609 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)3610 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3611 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313612 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 4, implicit-def $scc3613 ; CHECK-NEXT: S_ENDPGM 03614 %ptr = load ptr addrspace(1), ptr addrspace(4) poison3615 %val = load <32 x i32>, ptr addrspace(1) %ptr3616 call void @external_void_func_v32i32(<32 x i32> %val)3617 ret void3618}3619 3620define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {3621 ; CHECK-LABEL: name: test_call_external_void_func_v32i32_i323622 ; CHECK: bb.1 (%ir-block.1):3623 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113624 ; CHECK-NEXT: {{ $}}3625 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23626 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13627 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03628 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163629 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153630 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143631 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113632 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73633 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53634 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93635 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3636 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF3637 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)3638 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3639 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<32 x s32>) from %ir.ptr0, addrspace 1)3640 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p1) :: ("amdgpu-noclobber" load (s32) from `ptr addrspace(1) poison`, addrspace 1)3641 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3642 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_i323643 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3644 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3645 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3646 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 43647 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3648 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3649 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3650 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3651 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3652 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3653 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3654 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3655 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103656 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3657 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3658 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3659 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203660 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3661 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3662 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)3663 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg3664 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 03665 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)3666 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack, align 16, addrspace 5)3667 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 43668 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)3669 ; CHECK-NEXT: G_STORE [[LOAD2]](s32), [[PTR_ADD2]](p5) :: (store (s32) into stack + 4, addrspace 5)3670 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3671 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3672 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3673 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3674 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3675 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3676 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3677 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3678 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)3679 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)3680 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)3681 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)3682 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)3683 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)3684 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)3685 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)3686 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)3687 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)3688 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)3689 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)3690 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)3691 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)3692 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)3693 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)3694 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)3695 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)3696 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)3697 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)3698 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)3699 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)3700 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)3701 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3702 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3703 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3704 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3705 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3706 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3707 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3708 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3709 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3710 ; CHECK-NEXT: $sgpr15 = COPY [[DEF2]](s32)3711 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3712 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313713 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc3714 ; CHECK-NEXT: S_ENDPGM 03715 %ptr0 = load ptr addrspace(1), ptr addrspace(4) poison3716 %val0 = load <32 x i32>, ptr addrspace(1) %ptr03717 %val1 = load i32, ptr addrspace(1) poison3718 call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1)3719 ret void3720}3721 3722define amdgpu_kernel void @test_call_external_void_func_v32i32_i8_i8_i16() #0 {3723 ; CHECK-LABEL: name: test_call_external_void_func_v32i32_i8_i8_i163724 ; CHECK: bb.1 (%ir-block.0):3725 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113726 ; CHECK-NEXT: {{ $}}3727 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23728 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13729 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03730 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163731 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153732 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143733 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113734 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73735 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53736 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93737 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3738 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF3739 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3740 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<32 x s32>) from %ir.ptr0, addrspace 1)3741 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s8) = G_LOAD [[DEF1]](p1) :: ("amdgpu-noclobber" load (s8) from `ptr addrspace(1) poison`, addrspace 1)3742 ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s16) = G_LOAD [[DEF1]](p1) :: ("amdgpu-noclobber" load (s16) from `ptr addrspace(1) poison`, addrspace 1)3743 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3744 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_i8_i8_i163745 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3746 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3747 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3748 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 03749 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3750 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3751 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3752 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3753 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3754 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3755 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3756 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3757 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103758 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3759 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3760 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3761 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203762 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3763 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3764 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)3765 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg3766 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 03767 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)3768 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack, align 16, addrspace 5)3769 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD2]](s8)3770 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 43771 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)3772 ; CHECK-NEXT: G_STORE [[ANYEXT]](s16), [[PTR_ADD2]](p5) :: (store (s16) into stack + 4, align 4, addrspace 5)3773 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s16) = COPY [[ANYEXT]](s16)3774 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 83775 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](s32)3776 ; CHECK-NEXT: G_STORE [[COPY20]](s16), [[PTR_ADD3]](p5) :: (store (s16) into stack + 8, align 8, addrspace 5)3777 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 123778 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)3779 ; CHECK-NEXT: G_STORE [[LOAD3]](s16), [[PTR_ADD4]](p5) :: (store (s16) into stack + 12, align 4, addrspace 5)3780 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3781 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3782 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3783 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3784 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3785 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3786 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3787 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3788 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)3789 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)3790 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)3791 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)3792 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)3793 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)3794 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)3795 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)3796 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)3797 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)3798 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)3799 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)3800 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)3801 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)3802 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)3803 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)3804 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)3805 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)3806 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)3807 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)3808 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)3809 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)3810 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)3811 ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3812 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)3813 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3814 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3815 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3816 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3817 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3818 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3819 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3820 ; CHECK-NEXT: $sgpr15 = COPY [[DEF2]](s32)3821 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3822 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32_i8_i8_i16, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313823 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 16, implicit-def $scc3824 ; CHECK-NEXT: S_ENDPGM 03825 %ptr0 = load ptr addrspace(1), ptr addrspace(4) poison3826 %val0 = load <32 x i32>, ptr addrspace(1) %ptr03827 %val1 = load i8, ptr addrspace(1) poison3828 %val2 = load i8, ptr addrspace(1) poison3829 %val3 = load i16, ptr addrspace(1) poison3830 call void @external_void_func_v32i32_i8_i8_i16(<32 x i32> %val0, i8 %val1, i8 %val2, i16 %val3)3831 ret void3832}3833 3834define amdgpu_kernel void @test_call_external_void_func_v32i32_p3_p5() #0 {3835 ; CHECK-LABEL: name: test_call_external_void_func_v32i32_p3_p53836 ; CHECK: bb.1 (%ir-block.0):3837 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113838 ; CHECK-NEXT: {{ $}}3839 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23840 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13841 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03842 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163843 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153844 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143845 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113846 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73847 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53848 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93849 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3850 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF3851 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3852 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<32 x s32>) from %ir.ptr0, addrspace 1)3853 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[DEF1]](p1) :: ("amdgpu-noclobber" load (s32) from `ptr addrspace(1) poison`, addrspace 1)3854 ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[LOAD2]](s32)3855 ; CHECK-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p5) = G_INTTOPTR [[LOAD2]](s32)3856 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3857 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v32i32_p3_p53858 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3859 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3860 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3861 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 03862 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)3863 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3864 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3865 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3866 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3867 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3868 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3869 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3870 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 103871 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)3872 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3873 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3874 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 203875 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)3876 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3877 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](<32 x s32>)3878 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg3879 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 03880 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)3881 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack, align 16, addrspace 5)3882 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 43883 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)3884 ; CHECK-NEXT: G_STORE [[INTTOPTR]](p3), [[PTR_ADD2]](p5) :: (store (p3) into stack + 4, addrspace 5)3885 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 83886 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](s32)3887 ; CHECK-NEXT: G_STORE [[INTTOPTR1]](p5), [[PTR_ADD3]](p5) :: (store (p5) into stack + 8, align 8, addrspace 5)3888 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)3889 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)3890 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)3891 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)3892 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)3893 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)3894 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)3895 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)3896 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)3897 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)3898 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)3899 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)3900 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)3901 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)3902 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)3903 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)3904 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)3905 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)3906 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)3907 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)3908 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)3909 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)3910 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)3911 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)3912 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)3913 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)3914 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)3915 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)3916 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)3917 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)3918 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)3919 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3920 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3921 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3922 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3923 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)3924 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3925 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3926 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3927 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3928 ; CHECK-NEXT: $sgpr15 = COPY [[DEF2]](s32)3929 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3930 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v32i32_p3_p5, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313931 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 12, implicit-def $scc3932 ; CHECK-NEXT: S_ENDPGM 03933 %ptr0 = load ptr addrspace(1), ptr addrspace(4) poison3934 %val0 = load <32 x i32>, ptr addrspace(1) %ptr03935 %val1 = load ptr addrspace(3), ptr addrspace(1) poison3936 %val2 = load ptr addrspace(5), ptr addrspace(1) poison3937 call void @external_void_func_v32i32_p3_p5(<32 x i32> %val0, ptr addrspace(3) %val1, ptr addrspace(5) %val2)3938 ret void3939}3940 3941define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {3942 ; CHECK-LABEL: name: test_call_external_void_func_struct_i8_i323943 ; CHECK: bb.1 (%ir-block.0):3944 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr113945 ; CHECK-NEXT: {{ $}}3946 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr23947 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr13948 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr03949 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr163950 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr153951 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr143952 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr113953 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr73954 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr53955 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr93956 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF3957 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)3958 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (s8) from %ir.ptr0, align 4, addrspace 1)3959 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 43960 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[LOAD]], [[C]](s64)3961 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: ("amdgpu-noclobber" load (s32) from %ir.ptr0 + 4, addrspace 1)3962 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc3963 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_struct_i8_i323964 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]3965 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]3966 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)3967 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 03968 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)3969 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]3970 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]3971 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]3972 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]3973 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF3974 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)3975 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)3976 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 103977 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)3978 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]3979 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)3980 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 203981 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)3982 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]3983 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)3984 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)3985 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)3986 ; CHECK-NEXT: $vgpr1 = COPY [[LOAD2]](s32)3987 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg3988 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)3989 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)3990 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)3991 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)3992 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)3993 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)3994 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)3995 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)3996 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)3997 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)3998 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_struct_i8_i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr313999 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4000 ; CHECK-NEXT: S_ENDPGM 04001 %ptr0 = load ptr addrspace(1), ptr addrspace(4) poison4002 %val = load { i8, i32 }, ptr addrspace(1) %ptr04003 call void @external_void_func_struct_i8_i32({ i8, i32 } %val)4004 ret void4005}4006 4007define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32() #0 {4008 ; CHECK-LABEL: name: test_gfx_call_external_void_func_struct_i8_i324009 ; CHECK: bb.1 (%ir-block.0):4010 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4011 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4012 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load (s8) from %ir.ptr0, align 4, addrspace 1)4013 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 44014 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[LOAD]], [[C]](s64)4015 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32) from %ir.ptr0 + 4, addrspace 1)4016 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4017 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i324018 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)4019 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4020 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT1]](s32)4021 ; CHECK-NEXT: $vgpr1 = COPY [[LOAD2]](s32)4022 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr34023 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)4024 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr34025 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4026 ; CHECK-NEXT: SI_RETURN4027 %ptr0 = load ptr addrspace(1), ptr addrspace(4) poison4028 %val = load { i8, i32 }, ptr addrspace(1) %ptr04029 call amdgpu_gfx void @external_gfx_void_func_struct_i8_i32({ i8, i32 } %val)4030 ret void4031}4032 4033define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() #0 {4034 ; CHECK-LABEL: name: test_gfx_call_external_void_func_struct_i8_i32_inreg4035 ; CHECK: bb.1 (%ir-block.0):4036 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4037 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4038 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p1) :: (load (s8) from %ir.ptr0, align 4, addrspace 1)4039 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 44040 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = nuw inbounds G_PTR_ADD [[LOAD]], [[C]](s64)4041 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32) from %ir.ptr0 + 4, addrspace 1)4042 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4043 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg4044 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8)4045 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4046 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](s32)4047 ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32)4048 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[LOAD2]](s32)4049 ; CHECK-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT1]](s32)4050 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr34051 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>)4052 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr34053 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4054 ; CHECK-NEXT: SI_RETURN4055 %ptr0 = load ptr addrspace(1), ptr addrspace(4) poison4056 %val = load { i8, i32 }, ptr addrspace(1) %ptr04057 call amdgpu_gfx void @external_gfx_void_func_struct_i8_i32_inreg({ i8, i32 } inreg %val)4058 ret void4059}4060 4061define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {4062 ; CHECK-LABEL: name: test_call_external_void_func_byval_struct_i8_i324063 ; CHECK: bb.1 (%ir-block.0):4064 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114065 ; CHECK-NEXT: {{ $}}4066 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24067 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14068 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04069 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164070 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154071 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144072 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114073 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74074 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54075 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94076 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 34077 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 84078 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0.val4079 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 44080 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = nuw nusw inbounds G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32)4081 ; CHECK-NEXT: G_STORE [[C]](s8), [[FRAME_INDEX]](p5) :: (store (s8) into %ir.val, addrspace 5)4082 ; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p5) :: (store (s32) into %ir.gep1, addrspace 5)4083 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4084 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_byval_struct_i8_i324085 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4086 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4087 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4088 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 04089 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C3]](s64)4090 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4091 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4092 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4093 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4094 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4095 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4096 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4097 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 104098 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C4]](s32)4099 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4100 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4101 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 204102 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C5]](s32)4103 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4104 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg4105 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 04106 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)4107 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 84108 ; CHECK-NEXT: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](s32), 0 :: (dereferenceable store (s64) into stack, align 4, addrspace 5), (dereferenceable load (s64) from %ir.val, align 4, addrspace 5)4109 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4110 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4111 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4112 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4113 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)4114 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4115 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4116 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4117 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4118 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)4119 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4120 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_byval_struct_i8_i32, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314121 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 8, implicit-def $scc4122 ; CHECK-NEXT: S_ENDPGM 04123 %val = alloca { i8, i32 }, align 4, addrspace(5)4124 %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 04125 %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 14126 store i8 3, ptr addrspace(5) %gep04127 store i32 8, ptr addrspace(5) %gep14128 call void @external_void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 }) %val)4129 ret void4130}4131 4132declare void @void_func_byval_a3i32_byval_i8_align32(ptr addrspace(5) byval([3 x i32]) %arg0, ptr addrspace(5) byval(i8) align 32 %arg1, i32 %arg2) #04133 4134define void @call_byval_3ai32_byval_i8_align32(ptr addrspace(5) %incoming0, ptr addrspace(5) align 32 %incoming1) #0 {4135 ; CHECK-LABEL: name: call_byval_3ai32_byval_i8_align324136 ; CHECK: bb.1 (%ir-block.0):4137 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr1, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114138 ; CHECK-NEXT: {{ $}}4139 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr314140 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr154141 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr144142 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr134143 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr124144 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114145 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr94146 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74147 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54148 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p5) = COPY $vgpr04149 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p5) = COPY $vgpr14150 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 9994151 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4152 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @void_func_byval_a3i32_byval_i8_align324153 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]4154 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]4155 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]4156 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]4157 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4158 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4159 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]4160 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]4161 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4162 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr324163 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 04164 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C1]](s32)4165 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 124166 ; CHECK-NEXT: G_MEMCPY [[PTR_ADD]](p5), [[COPY9]](p5), [[C2]](s32), 0 :: (dereferenceable store (s96) into stack, align 4, addrspace 5), (dereferenceable load (s96) from %ir.incoming0, align 4, addrspace 5)4167 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 324168 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C3]](s32)4169 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 14170 ; CHECK-NEXT: G_MEMCPY [[PTR_ADD1]](p5), [[COPY10]](p5), [[C4]](s32), 0 :: (dereferenceable store (s8) into stack + 32, align 32, addrspace 5), (dereferenceable load (s8) from %ir.incoming1, align 32, addrspace 5)4171 ; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)4172 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr34173 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4174 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)4175 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)4176 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)4177 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)4178 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)4179 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)4180 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)4181 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)4182 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)4183 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @void_func_byval_a3i32_byval_i8_align32, csr_amdgpu, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314184 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 36, implicit-def $scc4185 ; CHECK-NEXT: SI_RETURN4186 call void @void_func_byval_a3i32_byval_i8_align32(ptr addrspace(5) byval([3 x i32]) %incoming0, ptr addrspace(5) align 32 %incoming1, i32 999)4187 ret void4188}4189 4190declare void @void_func_byval_a4i64_align4(ptr addrspace(5) byval([4 x i64]) align 4 %arg0) #04191 4192; Make sure we are aware of the higher alignment of the incoming value4193; than implied by the outgoing byval alignment in the memory operand.4194define void @call_byval_a4i64_align4_higher_source_align(ptr addrspace(5) align 256 %incoming_high_align) #0 {4195 ; CHECK-LABEL: name: call_byval_a4i64_align4_higher_source_align4196 ; CHECK: bb.1 (%ir-block.0):4197 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr0, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114198 ; CHECK-NEXT: {{ $}}4199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr314200 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr154201 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr144202 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr134203 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr124204 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114205 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr94206 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74207 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54208 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p5) = COPY $vgpr04209 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4210 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @void_func_byval_a4i64_align44211 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4212 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4213 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]4214 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]4215 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]4216 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]4217 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]4218 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]4219 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4220 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr324221 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 04222 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C]](s32)4223 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 324224 ; CHECK-NEXT: G_MEMCPY [[PTR_ADD]](p5), [[COPY9]](p5), [[C1]](s32), 0 :: (dereferenceable store (s256) into stack, align 4, addrspace 5), (dereferenceable load (s256) from %ir.incoming_high_align, align 256, addrspace 5)4225 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr34226 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)4227 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4228 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4229 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)4230 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4231 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4232 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4233 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4234 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)4235 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)4236 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @void_func_byval_a4i64_align4, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314237 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 32, implicit-def $scc4238 ; CHECK-NEXT: SI_RETURN4239 call void @void_func_byval_a4i64_align4(ptr addrspace(5) byval([4 x i64]) align 4 %incoming_high_align)4240 ret void4241}4242 4243define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 {4244 ; CHECK-LABEL: name: test_call_external_void_func_v2i84245 ; CHECK: bb.1 (%ir-block.0):4246 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114247 ; CHECK-NEXT: {{ $}}4248 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24249 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14250 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04251 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164252 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154253 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144254 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114255 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74256 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54257 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94258 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4259 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4260 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<2 x s8>) from %ir.ptr, addrspace 1)4261 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4262 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i84263 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4264 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4265 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4266 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 04267 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)4268 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4269 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4270 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4271 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4272 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4273 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4274 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4275 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 104276 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)4277 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4278 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4279 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 204280 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)4281 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4282 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<2 x s8>)4283 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)4284 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)4285 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4286 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT2]](s32)4287 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)4288 ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT3]](s32)4289 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4290 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4291 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4292 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4293 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)4294 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4295 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4296 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4297 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4298 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)4299 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4300 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314301 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4302 ; CHECK-NEXT: S_ENDPGM 04303 %ptr = load ptr addrspace(1), ptr addrspace(4) poison4304 %val = load <2 x i8>, ptr addrspace(1) %ptr4305 call void @external_void_func_v2i8(<2 x i8> %val)4306 ret void4307}4308 4309define amdgpu_kernel void @test_call_external_void_func_v3i8() #0 {4310 ; CHECK-LABEL: name: test_call_external_void_func_v3i84311 ; CHECK: bb.1 (%ir-block.0):4312 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114313 ; CHECK-NEXT: {{ $}}4314 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24315 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14316 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04317 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164318 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154319 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144320 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114321 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74322 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54323 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94324 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4325 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4326 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<3 x s8>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<3 x s8>) from %ir.ptr, align 4, addrspace 1)4327 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4328 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3i84329 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4330 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4331 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4332 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 04333 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)4334 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4335 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4336 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4337 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4338 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4339 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4340 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4341 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 104342 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)4343 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4344 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4345 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 204346 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)4347 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4348 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<3 x s8>)4349 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)4350 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)4351 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)4352 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4353 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT3]](s32)4354 ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)4355 ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT4]](s32)4356 ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)4357 ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT5]](s32)4358 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4359 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4360 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4361 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4362 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)4363 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4364 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4365 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4366 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4367 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)4368 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4369 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314370 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4371 ; CHECK-NEXT: S_ENDPGM 04372 %ptr = load ptr addrspace(1), ptr addrspace(4) poison4373 %val = load <3 x i8>, ptr addrspace(1) %ptr4374 call void @external_void_func_v3i8(<3 x i8> %val)4375 ret void4376}4377 4378define amdgpu_kernel void @test_call_external_void_func_v4i8() #0 {4379 ; CHECK-LABEL: name: test_call_external_void_func_v4i84380 ; CHECK: bb.1 (%ir-block.0):4381 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114382 ; CHECK-NEXT: {{ $}}4383 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24384 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14385 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04386 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164387 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154388 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144389 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114390 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74391 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54392 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94393 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4394 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4395 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<4 x s8>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<4 x s8>) from %ir.ptr, addrspace 1)4396 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4397 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4i84398 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4399 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4400 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4401 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 04402 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)4403 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4404 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4405 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4406 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4407 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4408 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4409 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4410 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 104411 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)4412 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4413 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4414 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 204415 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)4416 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4417 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<4 x s8>)4418 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)4419 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)4420 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)4421 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)4422 ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4423 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT4]](s32)4424 ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)4425 ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT5]](s32)4426 ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)4427 ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT6]](s32)4428 ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)4429 ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT7]](s32)4430 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4431 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4432 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4433 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4434 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)4435 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4436 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4437 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4438 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4439 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)4440 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4441 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314442 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4443 ; CHECK-NEXT: S_ENDPGM 04444 %ptr = load ptr addrspace(1), ptr addrspace(4) poison4445 %val = load <4 x i8>, ptr addrspace(1) %ptr4446 call void @external_void_func_v4i8(<4 x i8> %val)4447 ret void4448}4449 4450define amdgpu_kernel void @test_call_external_void_func_v8i8() #0 {4451 ; CHECK-LABEL: name: test_call_external_void_func_v8i84452 ; CHECK: bb.1 (%ir-block.0):4453 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114454 ; CHECK-NEXT: {{ $}}4455 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24456 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14457 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04458 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164459 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154460 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144461 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114462 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74463 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54464 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94465 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4466 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4467 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<8 x s8>) from %ir.ptr, addrspace 1)4468 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4469 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v8i84470 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4471 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4472 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4473 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 04474 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)4475 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4476 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4477 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4478 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4479 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4480 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4481 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4482 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 104483 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)4484 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4485 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4486 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 204487 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)4488 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4489 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<8 x s8>)4490 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)4491 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)4492 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)4493 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)4494 ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)4495 ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)4496 ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)4497 ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)4498 ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4499 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT8]](s32)4500 ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)4501 ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT9]](s32)4502 ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)4503 ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT10]](s32)4504 ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)4505 ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT11]](s32)4506 ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT4]](s16)4507 ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT12]](s32)4508 ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT5]](s16)4509 ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT13]](s32)4510 ; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT6]](s16)4511 ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT14]](s32)4512 ; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT7]](s16)4513 ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT15]](s32)4514 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4515 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4516 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4517 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4518 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)4519 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4520 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4521 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4522 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4523 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)4524 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4525 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v8i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314526 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4527 ; CHECK-NEXT: S_ENDPGM 04528 %ptr = load ptr addrspace(1), ptr addrspace(4) poison4529 %val = load <8 x i8>, ptr addrspace(1) %ptr4530 call void @external_void_func_v8i8(<8 x i8> %val)4531 ret void4532}4533 4534define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {4535 ; CHECK-LABEL: name: test_call_external_void_func_v16i84536 ; CHECK: bb.1 (%ir-block.0):4537 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114538 ; CHECK-NEXT: {{ $}}4539 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24540 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14541 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04542 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164543 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154544 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144545 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114546 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74547 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54548 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94549 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF4550 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[DEF]](p4) :: (invariant load (p1) from `ptr addrspace(4) poison`, addrspace 4)4551 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[LOAD]](p1) :: ("amdgpu-noclobber" load (<16 x s8>) from %ir.ptr, addrspace 1)4552 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4553 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v16i84554 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4555 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4556 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4557 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 04558 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C]](s64)4559 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4560 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4561 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4562 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4563 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4564 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4565 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4566 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 104567 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s32)4568 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4569 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4570 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 204571 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C2]](s32)4572 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4573 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[LOAD1]](<16 x s8>)4574 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[UV]](s8)4575 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[UV1]](s8)4576 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[UV2]](s8)4577 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s16) = G_ANYEXT [[UV3]](s8)4578 ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s16) = G_ANYEXT [[UV4]](s8)4579 ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s16) = G_ANYEXT [[UV5]](s8)4580 ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s16) = G_ANYEXT [[UV6]](s8)4581 ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s16) = G_ANYEXT [[UV7]](s8)4582 ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s16) = G_ANYEXT [[UV8]](s8)4583 ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s16) = G_ANYEXT [[UV9]](s8)4584 ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s16) = G_ANYEXT [[UV10]](s8)4585 ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s16) = G_ANYEXT [[UV11]](s8)4586 ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(s16) = G_ANYEXT [[UV12]](s8)4587 ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(s16) = G_ANYEXT [[UV13]](s8)4588 ; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(s16) = G_ANYEXT [[UV14]](s8)4589 ; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(s16) = G_ANYEXT [[UV15]](s8)4590 ; CHECK-NEXT: [[ANYEXT16:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16)4591 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT16]](s32)4592 ; CHECK-NEXT: [[ANYEXT17:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT1]](s16)4593 ; CHECK-NEXT: $vgpr1 = COPY [[ANYEXT17]](s32)4594 ; CHECK-NEXT: [[ANYEXT18:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT2]](s16)4595 ; CHECK-NEXT: $vgpr2 = COPY [[ANYEXT18]](s32)4596 ; CHECK-NEXT: [[ANYEXT19:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT3]](s16)4597 ; CHECK-NEXT: $vgpr3 = COPY [[ANYEXT19]](s32)4598 ; CHECK-NEXT: [[ANYEXT20:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT4]](s16)4599 ; CHECK-NEXT: $vgpr4 = COPY [[ANYEXT20]](s32)4600 ; CHECK-NEXT: [[ANYEXT21:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT5]](s16)4601 ; CHECK-NEXT: $vgpr5 = COPY [[ANYEXT21]](s32)4602 ; CHECK-NEXT: [[ANYEXT22:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT6]](s16)4603 ; CHECK-NEXT: $vgpr6 = COPY [[ANYEXT22]](s32)4604 ; CHECK-NEXT: [[ANYEXT23:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT7]](s16)4605 ; CHECK-NEXT: $vgpr7 = COPY [[ANYEXT23]](s32)4606 ; CHECK-NEXT: [[ANYEXT24:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT8]](s16)4607 ; CHECK-NEXT: $vgpr8 = COPY [[ANYEXT24]](s32)4608 ; CHECK-NEXT: [[ANYEXT25:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT9]](s16)4609 ; CHECK-NEXT: $vgpr9 = COPY [[ANYEXT25]](s32)4610 ; CHECK-NEXT: [[ANYEXT26:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT10]](s16)4611 ; CHECK-NEXT: $vgpr10 = COPY [[ANYEXT26]](s32)4612 ; CHECK-NEXT: [[ANYEXT27:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT11]](s16)4613 ; CHECK-NEXT: $vgpr11 = COPY [[ANYEXT27]](s32)4614 ; CHECK-NEXT: [[ANYEXT28:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT12]](s16)4615 ; CHECK-NEXT: $vgpr12 = COPY [[ANYEXT28]](s32)4616 ; CHECK-NEXT: [[ANYEXT29:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT13]](s16)4617 ; CHECK-NEXT: $vgpr13 = COPY [[ANYEXT29]](s32)4618 ; CHECK-NEXT: [[ANYEXT30:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT14]](s16)4619 ; CHECK-NEXT: $vgpr14 = COPY [[ANYEXT30]](s32)4620 ; CHECK-NEXT: [[ANYEXT31:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT15]](s16)4621 ; CHECK-NEXT: $vgpr15 = COPY [[ANYEXT31]](s32)4622 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4623 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4624 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4625 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4626 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD]](p4)4627 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4628 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4629 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4630 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4631 ; CHECK-NEXT: $sgpr15 = COPY [[DEF1]](s32)4632 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4633 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v16i8, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314634 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc4635 ; CHECK-NEXT: S_ENDPGM 04636 %ptr = load ptr addrspace(1), ptr addrspace(4) poison4637 %val = load <16 x i8>, ptr addrspace(1) %ptr4638 call void @external_void_func_v16i8(<16 x i8> %val)4639 ret void4640}4641 4642define amdgpu_kernel void @stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {4643 ; CHECK-LABEL: name: stack_passed_arg_alignment_v32i32_f644644 ; CHECK: bb.1.entry:4645 ; CHECK-NEXT: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114646 ; CHECK-NEXT: {{ $}}4647 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr24648 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr14649 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr04650 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr164651 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr154652 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr144653 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114654 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74655 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54656 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr94657 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)4658 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<32 x s32>) = G_LOAD [[INT]](p4) :: (dereferenceable invariant load (<32 x s32>) from %ir.val.kernarg.offset1, align 16, addrspace 4)4659 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1284660 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p4) = nuw nusw inbounds G_PTR_ADD [[INT]], [[C]](s64)4661 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p4) :: (dereferenceable invariant load (s64) from %ir.tmp.kernarg.offset, align 16, addrspace 4)4662 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4663 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @stack_passed_f64_arg4664 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]4665 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]4666 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)4667 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1364668 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p4) = nuw inbounds G_PTR_ADD [[COPY12]], [[C1]](s64)4669 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY6]]4670 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY5]]4671 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]4672 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]4673 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF4674 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)4675 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)4676 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 104677 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C2]](s32)4678 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY17]], [[SHL]]4679 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4680 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 204681 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C3]](s32)4682 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]4683 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<32 x s32>)4684 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sp_reg4685 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 04686 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C4]](s32)4687 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD2]](p5) :: (store (s32) into stack, align 16, addrspace 5)4688 ; CHECK-NEXT: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](s64)4689 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 44690 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C5]](s32)4691 ; CHECK-NEXT: G_STORE [[UV32]](s32), [[PTR_ADD3]](p5) :: (store (s32) into stack + 4, addrspace 5)4692 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 84693 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C6]](s32)4694 ; CHECK-NEXT: G_STORE [[UV33]](s32), [[PTR_ADD4]](p5) :: (store (s32) into stack + 8, align 8, addrspace 5)4695 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)4696 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)4697 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)4698 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)4699 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)4700 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)4701 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)4702 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)4703 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)4704 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)4705 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)4706 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)4707 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)4708 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)4709 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)4710 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)4711 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)4712 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)4713 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)4714 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)4715 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)4716 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)4717 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)4718 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)4719 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)4720 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)4721 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)4722 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)4723 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)4724 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)4725 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)4726 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg4727 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)4728 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)4729 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)4730 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)4731 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)4732 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)4733 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)4734 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)4735 ; CHECK-NEXT: $sgpr15 = COPY [[DEF]](s32)4736 ; CHECK-NEXT: $vgpr31 = COPY [[OR1]](s32)4737 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @stack_passed_f64_arg, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314738 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 12, implicit-def $scc4739 ; CHECK-NEXT: S_ENDPGM 04740entry:4741 call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)4742 ret void4743}4744 4745define void @stack_12xv3i32() #0 {4746 ; CHECK-LABEL: name: stack_12xv3i324747 ; CHECK: bb.1.entry:4748 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114749 ; CHECK-NEXT: {{ $}}4750 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr314751 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr154752 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr144753 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr134754 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr124755 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114756 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr94757 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74758 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54759 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 04760 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32)4761 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 14762 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32)4763 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24764 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32), [[C2]](s32)4765 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 34766 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32)4767 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 44768 ; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32)4769 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 54770 ; CHECK-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C5]](s32), [[C5]](s32), [[C5]](s32)4771 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 64772 ; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C6]](s32), [[C6]](s32)4773 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 74774 ; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C7]](s32), [[C7]](s32), [[C7]](s32)4775 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 84776 ; CHECK-NEXT: [[BUILD_VECTOR8:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C8]](s32), [[C8]](s32), [[C8]](s32)4777 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 94778 ; CHECK-NEXT: [[BUILD_VECTOR9:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C9]](s32), [[C9]](s32), [[C9]](s32)4779 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 104780 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 114781 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 124782 ; CHECK-NEXT: [[BUILD_VECTOR10:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C10]](s32), [[C11]](s32), [[C12]](s32)4783 ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 134784 ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 144785 ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 154786 ; CHECK-NEXT: [[BUILD_VECTOR11:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C13]](s32), [[C14]](s32), [[C15]](s32)4787 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4788 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_12xv3i324789 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]4790 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]4791 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]4792 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY5]]4793 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]4794 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]4795 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]4796 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]4797 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4798 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)4799 ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x s32>)4800 ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x s32>)4801 ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)4802 ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<3 x s32>)4803 ; CHECK-NEXT: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<3 x s32>)4804 ; CHECK-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<3 x s32>)4805 ; CHECK-NEXT: [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<3 x s32>)4806 ; CHECK-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR8]](<3 x s32>)4807 ; CHECK-NEXT: [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x s32>)4808 ; CHECK-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x s32>)4809 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr324810 ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 04811 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)4812 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store (s32) into stack, align 16, addrspace 5)4813 ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 44814 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)4815 ; CHECK-NEXT: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack + 4, addrspace 5)4816 ; CHECK-NEXT: [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x s32>)4817 ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 84818 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)4819 ; CHECK-NEXT: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store (s32) into stack + 8, align 8, addrspace 5)4820 ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 124821 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)4822 ; CHECK-NEXT: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store (s32) into stack + 12, addrspace 5)4823 ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 164824 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)4825 ; CHECK-NEXT: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store (s32) into stack + 16, align 16, addrspace 5)4826 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)4827 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)4828 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)4829 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)4830 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)4831 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)4832 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)4833 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)4834 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)4835 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)4836 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)4837 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)4838 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)4839 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)4840 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)4841 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)4842 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)4843 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)4844 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)4845 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)4846 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)4847 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)4848 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)4849 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)4850 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)4851 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)4852 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)4853 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)4854 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)4855 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)4856 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)4857 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr34858 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)4859 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)4860 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)4861 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)4862 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)4863 ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)4864 ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)4865 ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)4866 ; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)4867 ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)4868 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_12xv3i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr314869 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 20, implicit-def $scc4870 ; CHECK-NEXT: SI_RETURN4871entry:4872 call void @external_void_func_12xv3i32(4873 <3 x i32> <i32 0, i32 0, i32 0>,4874 <3 x i32> <i32 1, i32 1, i32 1>,4875 <3 x i32> <i32 2, i32 2, i32 2>,4876 <3 x i32> <i32 3, i32 3, i32 3>,4877 <3 x i32> <i32 4, i32 4, i32 4>,4878 <3 x i32> <i32 5, i32 5, i32 5>,4879 <3 x i32> <i32 6, i32 6, i32 6>,4880 <3 x i32> <i32 7, i32 7, i32 7>,4881 <3 x i32> <i32 8, i32 8, i32 8>,4882 <3 x i32> <i32 9, i32 9, i32 9>,4883 <3 x i32> <i32 10, i32 11, i32 12>,4884 <3 x i32> <i32 13, i32 14, i32 15>)4885 ret void4886}4887 4888define void @stack_12xv3f32() #0 {4889 ; CHECK-LABEL: name: stack_12xv3f324890 ; CHECK: bb.1.entry:4891 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr114892 ; CHECK-NEXT: {{ $}}4893 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr314894 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr154895 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr144896 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr134897 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr124898 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr114899 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr94900 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr74901 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr54902 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+004903 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32)4904 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+004905 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32)4906 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+004907 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32), [[C2]](s32)4908 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+004909 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32)4910 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+004911 ; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32)4912 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+004913 ; CHECK-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C5]](s32), [[C5]](s32), [[C5]](s32)4914 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+004915 ; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C6]](s32), [[C6]](s32)4916 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+004917 ; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C7]](s32), [[C7]](s32), [[C7]](s32)4918 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+004919 ; CHECK-NEXT: [[BUILD_VECTOR8:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C8]](s32), [[C8]](s32), [[C8]](s32)4920 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+004921 ; CHECK-NEXT: [[BUILD_VECTOR9:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C9]](s32), [[C9]](s32), [[C9]](s32)4922 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+014923 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+014924 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+014925 ; CHECK-NEXT: [[BUILD_VECTOR10:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C10]](s32), [[C11]](s32), [[C12]](s32)4926 ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+014927 ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.400000e+014928 ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+014929 ; CHECK-NEXT: [[BUILD_VECTOR11:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C13]](s32), [[C14]](s32), [[C15]](s32)4930 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc4931 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_12xv3f324932 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]4933 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]4934 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]4935 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY5]]4936 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]4937 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]4938 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]4939 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]4940 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)4941 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>)4942 ; CHECK-NEXT: [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<3 x s32>)4943 ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<3 x s32>)4944 ; CHECK-NEXT: [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<3 x s32>)4945 ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<3 x s32>)4946 ; CHECK-NEXT: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<3 x s32>)4947 ; CHECK-NEXT: [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<3 x s32>)4948 ; CHECK-NEXT: [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<3 x s32>)4949 ; CHECK-NEXT: [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR8]](<3 x s32>)4950 ; CHECK-NEXT: [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR9]](<3 x s32>)4951 ; CHECK-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR10]](<3 x s32>)4952 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr324953 ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 04954 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)4955 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store (s32) into stack, align 16, addrspace 5)4956 ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 44957 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)4958 ; CHECK-NEXT: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack + 4, addrspace 5)4959 ; CHECK-NEXT: [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR11]](<3 x s32>)4960 ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 84961 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)4962 ; CHECK-NEXT: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store (s32) into stack + 8, align 8, addrspace 5)4963 ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 124964 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)4965 ; CHECK-NEXT: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store (s32) into stack + 12, addrspace 5)4966 ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 164967 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)4968 ; CHECK-NEXT: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store (s32) into stack + 16, align 16, addrspace 5)4969 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)4970 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)4971 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)4972 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)4973 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)4974 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)4975 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)4976 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)4977 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)4978 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)4979 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)4980 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)4981 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)4982 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)4983 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)4984 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)4985 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)4986 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)4987 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)4988 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)4989 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)4990 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)4991 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)4992 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)4993 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)4994 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)4995 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)4996 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)4997 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)4998 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)4999 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)5000 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35001 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)5002 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)5003 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)5004 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)5005 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)5006 ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)5007 ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)5008 ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)5009 ; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)5010 ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)5011 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_12xv3f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315012 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 20, implicit-def $scc5013 ; CHECK-NEXT: SI_RETURN5014entry:5015 call void @external_void_func_12xv3f32(5016 <3 x float> <float 0.0, float 0.0, float 0.0>,5017 <3 x float> <float 1.0, float 1.0, float 1.0>,5018 <3 x float> <float 2.0, float 2.0, float 2.0>,5019 <3 x float> <float 3.0, float 3.0, float 3.0>,5020 <3 x float> <float 4.0, float 4.0, float 4.0>,5021 <3 x float> <float 5.0, float 5.0, float 5.0>,5022 <3 x float> <float 6.0, float 6.0, float 6.0>,5023 <3 x float> <float 7.0, float 7.0, float 7.0>,5024 <3 x float> <float 8.0, float 8.0, float 8.0>,5025 <3 x float> <float 9.0, float 9.0, float 9.0>,5026 <3 x float> <float 10.0, float 11.0, float 12.0>,5027 <3 x float> <float 13.0, float 14.0, float 15.0>)5028 ret void5029}5030 5031define void @stack_8xv5i32() #0 {5032 ; CHECK-LABEL: name: stack_8xv5i325033 ; CHECK: bb.1.entry:5034 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115035 ; CHECK-NEXT: {{ $}}5036 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315037 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155038 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145039 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135040 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125041 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115042 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95043 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75044 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55045 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 05046 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)5047 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15048 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)5049 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25050 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32), [[C2]](s32), [[C2]](s32), [[C2]](s32)5051 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 35052 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)5053 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 45054 ; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32)5055 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 55056 ; CHECK-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C5]](s32), [[C5]](s32), [[C5]](s32), [[C5]](s32), [[C5]](s32)5057 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65058 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 75059 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 85060 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 95061 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 105062 ; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C7]](s32), [[C8]](s32), [[C9]](s32), [[C10]](s32)5063 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 115064 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 125065 ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 135066 ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 145067 ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 155068 ; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C11]](s32), [[C12]](s32), [[C13]](s32), [[C14]](s32), [[C15]](s32)5069 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5070 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_8xv5i325071 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]5072 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]5073 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]5074 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY5]]5075 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]5076 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]5077 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]5078 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]5079 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5080 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)5081 ; CHECK-NEXT: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x s32>)5082 ; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x s32>)5083 ; CHECK-NEXT: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<5 x s32>)5084 ; CHECK-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<5 x s32>)5085 ; CHECK-NEXT: [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x s32>)5086 ; CHECK-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x s32>)5087 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr325088 ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 05089 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)5090 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store (s32) into stack, align 16, addrspace 5)5091 ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 45092 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)5093 ; CHECK-NEXT: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack + 4, addrspace 5)5094 ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 85095 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)5096 ; CHECK-NEXT: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store (s32) into stack + 8, align 8, addrspace 5)5097 ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 125098 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)5099 ; CHECK-NEXT: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store (s32) into stack + 12, addrspace 5)5100 ; CHECK-NEXT: [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x s32>)5101 ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 165102 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)5103 ; CHECK-NEXT: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store (s32) into stack + 16, align 16, addrspace 5)5104 ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 205105 ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C21]](s32)5106 ; CHECK-NEXT: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store (s32) into stack + 20, addrspace 5)5107 ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 245108 ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C22]](s32)5109 ; CHECK-NEXT: G_STORE [[UV37]](s32), [[PTR_ADD6]](p5) :: (store (s32) into stack + 24, align 8, addrspace 5)5110 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 285111 ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](s32)5112 ; CHECK-NEXT: G_STORE [[UV38]](s32), [[PTR_ADD7]](p5) :: (store (s32) into stack + 28, addrspace 5)5113 ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 325114 ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C24]](s32)5115 ; CHECK-NEXT: G_STORE [[UV39]](s32), [[PTR_ADD8]](p5) :: (store (s32) into stack + 32, align 16, addrspace 5)5116 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)5117 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)5118 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)5119 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)5120 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)5121 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)5122 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)5123 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)5124 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)5125 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)5126 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)5127 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)5128 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)5129 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)5130 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)5131 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)5132 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)5133 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)5134 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)5135 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)5136 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)5137 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)5138 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)5139 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)5140 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)5141 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)5142 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)5143 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)5144 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)5145 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)5146 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)5147 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35148 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)5149 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)5150 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)5151 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)5152 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)5153 ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)5154 ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)5155 ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)5156 ; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)5157 ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)5158 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_8xv5i32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315159 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 36, implicit-def $scc5160 ; CHECK-NEXT: SI_RETURN5161entry:5162 call void @external_void_func_8xv5i32(5163 <5 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0>,5164 <5 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1>,5165 <5 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2>,5166 <5 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3>,5167 <5 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4>,5168 <5 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5>,5169 <5 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10>,5170 <5 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15>)5171 ret void5172}5173 5174define void @stack_8xv5f32() #0 {5175 ; CHECK-LABEL: name: stack_8xv5f325176 ; CHECK: bb.1.entry:5177 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115178 ; CHECK-NEXT: {{ $}}5179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315180 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155181 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145182 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135183 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125184 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115185 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95186 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75187 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55188 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+005189 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)5190 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+005191 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)5192 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+005193 ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32), [[C2]](s32), [[C2]](s32), [[C2]](s32)5194 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 3.000000e+005195 ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32), [[C3]](s32)5196 ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 4.000000e+005197 ; CHECK-NEXT: [[BUILD_VECTOR4:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32)5198 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+005199 ; CHECK-NEXT: [[BUILD_VECTOR5:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C5]](s32), [[C5]](s32), [[C5]](s32), [[C5]](s32), [[C5]](s32)5200 ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 6.000000e+005201 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.000000e+005202 ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_FCONSTANT float 8.000000e+005203 ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_FCONSTANT float 9.000000e+005204 ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+015205 ; CHECK-NEXT: [[BUILD_VECTOR6:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C6]](s32), [[C7]](s32), [[C8]](s32), [[C9]](s32), [[C10]](s32)5206 ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.100000e+015207 ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.200000e+015208 ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.300000e+015209 ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.400000e+015210 ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.500000e+015211 ; CHECK-NEXT: [[BUILD_VECTOR7:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[C11]](s32), [[C12]](s32), [[C13]](s32), [[C14]](s32), [[C15]](s32)5212 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5213 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_8xv5f325214 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p4) = COPY [[COPY8]]5215 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]5216 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]5217 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY [[COPY5]]5218 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY4]]5219 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]5220 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]5221 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]5222 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5223 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<5 x s32>)5224 ; CHECK-NEXT: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<5 x s32>)5225 ; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR2]](<5 x s32>)5226 ; CHECK-NEXT: [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR3]](<5 x s32>)5227 ; CHECK-NEXT: [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR4]](<5 x s32>)5228 ; CHECK-NEXT: [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR5]](<5 x s32>)5229 ; CHECK-NEXT: [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32), [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR6]](<5 x s32>)5230 ; CHECK-NEXT: [[AMDGPU_WAVE_ADDRESS:%[0-9]+]]:_(p5) = G_AMDGPU_WAVE_ADDRESS $sgpr325231 ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 05232 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C16]](s32)5233 ; CHECK-NEXT: G_STORE [[UV31]](s32), [[PTR_ADD]](p5) :: (store (s32) into stack, align 16, addrspace 5)5234 ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 45235 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C17]](s32)5236 ; CHECK-NEXT: G_STORE [[UV32]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack + 4, addrspace 5)5237 ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 85238 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C18]](s32)5239 ; CHECK-NEXT: G_STORE [[UV33]](s32), [[PTR_ADD2]](p5) :: (store (s32) into stack + 8, align 8, addrspace 5)5240 ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 125241 ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C19]](s32)5242 ; CHECK-NEXT: G_STORE [[UV34]](s32), [[PTR_ADD3]](p5) :: (store (s32) into stack + 12, addrspace 5)5243 ; CHECK-NEXT: [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR7]](<5 x s32>)5244 ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 165245 ; CHECK-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C20]](s32)5246 ; CHECK-NEXT: G_STORE [[UV35]](s32), [[PTR_ADD4]](p5) :: (store (s32) into stack + 16, align 16, addrspace 5)5247 ; CHECK-NEXT: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 205248 ; CHECK-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C21]](s32)5249 ; CHECK-NEXT: G_STORE [[UV36]](s32), [[PTR_ADD5]](p5) :: (store (s32) into stack + 20, addrspace 5)5250 ; CHECK-NEXT: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 245251 ; CHECK-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C22]](s32)5252 ; CHECK-NEXT: G_STORE [[UV37]](s32), [[PTR_ADD6]](p5) :: (store (s32) into stack + 24, align 8, addrspace 5)5253 ; CHECK-NEXT: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 285254 ; CHECK-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C23]](s32)5255 ; CHECK-NEXT: G_STORE [[UV38]](s32), [[PTR_ADD7]](p5) :: (store (s32) into stack + 28, addrspace 5)5256 ; CHECK-NEXT: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 325257 ; CHECK-NEXT: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[AMDGPU_WAVE_ADDRESS]], [[C24]](s32)5258 ; CHECK-NEXT: G_STORE [[UV39]](s32), [[PTR_ADD8]](p5) :: (store (s32) into stack + 32, align 16, addrspace 5)5259 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)5260 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)5261 ; CHECK-NEXT: $vgpr2 = COPY [[UV2]](s32)5262 ; CHECK-NEXT: $vgpr3 = COPY [[UV3]](s32)5263 ; CHECK-NEXT: $vgpr4 = COPY [[UV4]](s32)5264 ; CHECK-NEXT: $vgpr5 = COPY [[UV5]](s32)5265 ; CHECK-NEXT: $vgpr6 = COPY [[UV6]](s32)5266 ; CHECK-NEXT: $vgpr7 = COPY [[UV7]](s32)5267 ; CHECK-NEXT: $vgpr8 = COPY [[UV8]](s32)5268 ; CHECK-NEXT: $vgpr9 = COPY [[UV9]](s32)5269 ; CHECK-NEXT: $vgpr10 = COPY [[UV10]](s32)5270 ; CHECK-NEXT: $vgpr11 = COPY [[UV11]](s32)5271 ; CHECK-NEXT: $vgpr12 = COPY [[UV12]](s32)5272 ; CHECK-NEXT: $vgpr13 = COPY [[UV13]](s32)5273 ; CHECK-NEXT: $vgpr14 = COPY [[UV14]](s32)5274 ; CHECK-NEXT: $vgpr15 = COPY [[UV15]](s32)5275 ; CHECK-NEXT: $vgpr16 = COPY [[UV16]](s32)5276 ; CHECK-NEXT: $vgpr17 = COPY [[UV17]](s32)5277 ; CHECK-NEXT: $vgpr18 = COPY [[UV18]](s32)5278 ; CHECK-NEXT: $vgpr19 = COPY [[UV19]](s32)5279 ; CHECK-NEXT: $vgpr20 = COPY [[UV20]](s32)5280 ; CHECK-NEXT: $vgpr21 = COPY [[UV21]](s32)5281 ; CHECK-NEXT: $vgpr22 = COPY [[UV22]](s32)5282 ; CHECK-NEXT: $vgpr23 = COPY [[UV23]](s32)5283 ; CHECK-NEXT: $vgpr24 = COPY [[UV24]](s32)5284 ; CHECK-NEXT: $vgpr25 = COPY [[UV25]](s32)5285 ; CHECK-NEXT: $vgpr26 = COPY [[UV26]](s32)5286 ; CHECK-NEXT: $vgpr27 = COPY [[UV27]](s32)5287 ; CHECK-NEXT: $vgpr28 = COPY [[UV28]](s32)5288 ; CHECK-NEXT: $vgpr29 = COPY [[UV29]](s32)5289 ; CHECK-NEXT: $vgpr30 = COPY [[UV30]](s32)5290 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35291 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY18]](<4 x s32>)5292 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY9]](p4)5293 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY10]](p4)5294 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY11]](p4)5295 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY12]](s64)5296 ; CHECK-NEXT: $sgpr12 = COPY [[COPY13]](s32)5297 ; CHECK-NEXT: $sgpr13 = COPY [[COPY14]](s32)5298 ; CHECK-NEXT: $sgpr14 = COPY [[COPY15]](s32)5299 ; CHECK-NEXT: $sgpr15 = COPY [[COPY16]](s32)5300 ; CHECK-NEXT: $vgpr31 = COPY [[COPY17]](s32)5301 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_8xv5f32, csr_amdgpu, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3, implicit $vgpr4, implicit $vgpr5, implicit $vgpr6, implicit $vgpr7, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $vgpr12, implicit $vgpr13, implicit $vgpr14, implicit $vgpr15, implicit $vgpr16, implicit $vgpr17, implicit $vgpr18, implicit $vgpr19, implicit $vgpr20, implicit $vgpr21, implicit $vgpr22, implicit $vgpr23, implicit $vgpr24, implicit $vgpr25, implicit $vgpr26, implicit $vgpr27, implicit $vgpr28, implicit $vgpr29, implicit $vgpr30, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315302 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 36, implicit-def $scc5303 ; CHECK-NEXT: SI_RETURN5304entry:5305 call void @external_void_func_8xv5f32(5306 <5 x float> <float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>,5307 <5 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>,5308 <5 x float> <float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>,5309 <5 x float> <float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>,5310 <5 x float> <float 4.0, float 4.0, float 4.0, float 4.0, float 4.0>,5311 <5 x float> <float 5.0, float 5.0, float 5.0, float 5.0, float 5.0>,5312 <5 x float> <float 6.0, float 7.0, float 8.0, float 9.0, float 10.0>,5313 <5 x float> <float 11.0, float 12.0, float 13.0, float 14.0, float 15.0>)5314 ret void5315}5316 5317define amdgpu_ps void @amdgpu_ps_call_default_cc() {5318 ; CHECK-LABEL: name: amdgpu_ps_call_default_cc5319 ; CHECK: bb.1.main_body:5320 ; CHECK-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 05321 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5322 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p4) = G_IMPLICIT_DEF5323 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY [[DEF]](p4)5324 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(p4) = G_CONSTANT i64 05325 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 05326 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p4) = COPY [[C1]](p4)5327 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF5328 ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF5329 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)5330 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)5331 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)5332 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[DEF2]](s32)5333 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg5334 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY6]](<4 x s32>)5335 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[DEF]](p4)5336 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY]](p4)5337 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY1]](p4)5338 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[DEF1]](s64)5339 ; CHECK-NEXT: $sgpr12 = COPY [[DEF2]](s32)5340 ; CHECK-NEXT: $sgpr13 = COPY [[COPY2]](s32)5341 ; CHECK-NEXT: $sgpr14 = COPY [[COPY3]](s32)5342 ; CHECK-NEXT: $sgpr15 = COPY [[COPY4]](s32)5343 ; CHECK-NEXT: $vgpr31 = COPY [[COPY5]](s32)5344 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[C]](p0), 0, csr_amdgpu, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315345 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5346 ; CHECK-NEXT: S_ENDPGM 05347main_body:5348 call void null()5349 ret void5350}5351 5352define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 {5353 ; CHECK-LABEL: name: test_call_external_void_func_i16_inreg5354 ; CHECK: bb.1 (%ir-block.0):5355 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115356 ; CHECK-NEXT: {{ $}}5357 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315358 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155359 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145360 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135361 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125362 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115363 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95364 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75365 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55366 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165367 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)5368 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5369 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i16_inreg5370 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]5371 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]5372 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]5373 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]5374 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]5375 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]5376 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]5377 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]5378 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5379 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)5380 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32)5381 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5382 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35383 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)5384 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)5385 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)5386 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)5387 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)5388 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)5389 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)5390 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)5391 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)5392 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)5393 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i16_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315394 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5395 ; CHECK-NEXT: SI_RETURN5396 call void @external_void_func_i16_inreg(i16 inreg %arg)5397 ret void5398}5399 5400define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 {5401 ; CHECK-LABEL: name: test_call_external_void_func_i32_inreg5402 ; CHECK: bb.1 (%ir-block.0):5403 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115404 ; CHECK-NEXT: {{ $}}5405 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315406 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155407 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145408 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135409 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125410 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115411 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95412 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75413 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55414 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165415 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5416 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i32_inreg5417 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]5418 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]5419 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]5420 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]5421 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]5422 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]5423 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]5424 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]5425 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5426 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32)5427 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5428 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35429 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)5430 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)5431 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)5432 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)5433 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)5434 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)5435 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)5436 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)5437 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)5438 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)5439 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i32_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315440 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5441 ; CHECK-NEXT: SI_RETURN5442 call void @external_void_func_i32_inreg(i32 inreg %arg)5443 ret void5444}5445 5446define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 {5447 ; CHECK-LABEL: name: test_call_external_void_func_i64_inreg5448 ; CHECK: bb.1 (%ir-block.0):5449 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115450 ; CHECK-NEXT: {{ $}}5451 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315452 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155453 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145454 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135455 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125456 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115457 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95458 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75459 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55460 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165461 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr175462 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)5463 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5464 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_i64_inreg5465 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5466 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5467 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5468 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5469 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5470 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5471 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5472 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5473 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5474 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)5475 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)5476 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5477 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)5478 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5479 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35480 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5481 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5482 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5483 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5484 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5485 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5486 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5487 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5488 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5489 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5490 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_i64_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315491 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5492 ; CHECK-NEXT: SI_RETURN5493 call void @external_void_func_i64_inreg(i64 inreg %arg)5494 ret void5495}5496 5497define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 {5498 ; CHECK-LABEL: name: test_call_external_void_func_v2i32_inreg5499 ; CHECK: bb.1 (%ir-block.0):5500 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115501 ; CHECK-NEXT: {{ $}}5502 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315503 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155504 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145505 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135506 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125507 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115508 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95509 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75510 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55511 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165512 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr175513 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32)5514 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5515 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2i32_inreg5516 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5517 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5518 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5519 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5520 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5521 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5522 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5523 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5524 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5525 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>)5526 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)5527 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5528 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)5529 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5530 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35531 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5532 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5533 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5534 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5535 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5536 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5537 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5538 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5539 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5540 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5541 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2i32_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315542 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5543 ; CHECK-NEXT: SI_RETURN5544 call void @external_void_func_v2i32_inreg(<2 x i32> inreg %arg)5545 ret void5546}5547 5548define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 {5549 ; CHECK-LABEL: name: test_call_external_void_func_f16_inreg5550 ; CHECK: bb.1 (%ir-block.0):5551 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115552 ; CHECK-NEXT: {{ $}}5553 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315554 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155555 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145556 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135557 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125558 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115559 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95560 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75561 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55562 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165563 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY9]](s32)5564 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5565 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f16_inreg5566 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]5567 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]5568 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]5569 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]5570 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]5571 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]5572 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]5573 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]5574 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5575 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)5576 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32)5577 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5578 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35579 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)5580 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)5581 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)5582 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)5583 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)5584 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)5585 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)5586 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)5587 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)5588 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)5589 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f16_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315590 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5591 ; CHECK-NEXT: SI_RETURN5592 call void @external_void_func_f16_inreg(half inreg %arg)5593 ret void5594}5595 5596define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 {5597 ; CHECK-LABEL: name: test_call_external_void_func_bf16_inreg5598 ; CHECK: bb.0:5599 ; CHECK-NEXT: successors: %bb.1(0x80000000)5600 ; CHECK-NEXT: liveins: $sgpr165601 ; CHECK-NEXT: {{ $}}5602 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr165603 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)5604 ; CHECK-NEXT: {{ $}}5605 ; CHECK-NEXT: bb.1 (%ir-block.0):5606 call void @external_void_func_bf16_inreg(bfloat inreg %arg)5607 ret void5608}5609 5610define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 {5611 ; CHECK-LABEL: name: test_call_external_void_func_f32_inreg5612 ; CHECK: bb.1 (%ir-block.0):5613 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115614 ; CHECK-NEXT: {{ $}}5615 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315616 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155617 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145618 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135619 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125620 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115621 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95622 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75623 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55624 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165625 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5626 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f32_inreg5627 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]5628 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]5629 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]5630 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]5631 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]5632 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]5633 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]5634 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]5635 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5636 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32)5637 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5638 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35639 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)5640 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)5641 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)5642 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)5643 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)5644 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)5645 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)5646 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)5647 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)5648 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)5649 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f32_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315650 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5651 ; CHECK-NEXT: SI_RETURN5652 call void @external_void_func_f32_inreg(float inreg %arg)5653 ret void5654}5655 5656define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 {5657 ; CHECK-LABEL: name: test_call_external_void_func_f64_inreg5658 ; CHECK: bb.1 (%ir-block.0):5659 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115660 ; CHECK-NEXT: {{ $}}5661 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315662 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155663 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145664 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135665 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125666 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115667 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95668 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75669 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55670 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165671 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr175672 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)5673 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5674 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_f64_inreg5675 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5676 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5677 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5678 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5679 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5680 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5681 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5682 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5683 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5684 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)5685 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)5686 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5687 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)5688 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5689 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35690 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5691 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5692 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5693 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5694 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5695 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5696 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5697 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5698 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5699 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5700 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_f64_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315701 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5702 ; CHECK-NEXT: SI_RETURN5703 call void @external_void_func_f64_inreg(double inreg %arg)5704 ret void5705}5706 5707define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0 {5708 ; CHECK-LABEL: name: test_call_external_void_func_v2f16_inreg5709 ; CHECK: bb.1 (%ir-block.0):5710 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115711 ; CHECK-NEXT: {{ $}}5712 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315713 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155714 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145715 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135716 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125717 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115718 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95719 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75720 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55721 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $sgpr165722 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5723 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2f16_inreg5724 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]5725 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]5726 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]5727 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]5728 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]5729 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]5730 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]5731 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]5732 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5733 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)5734 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)5735 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5736 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35737 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)5738 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)5739 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)5740 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)5741 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)5742 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)5743 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)5744 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)5745 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)5746 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)5747 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2f16_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315748 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5749 ; CHECK-NEXT: SI_RETURN5750 call void @external_void_func_v2f16_inreg(<2 x half> inreg %arg)5751 ret void5752}5753 5754define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0 {5755 ; CHECK-LABEL: name: test_call_external_void_func_v3f16_inreg5756 ; CHECK: bb.1 (%ir-block.0):5757 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115758 ; CHECK-NEXT: {{ $}}5759 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315760 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155761 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145762 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135763 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125764 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115765 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95766 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75767 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55768 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $sgpr165769 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $sgpr175770 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>)5771 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s16>)5772 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16)5773 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5774 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v3f16_inreg5775 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5776 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5777 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5778 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5779 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5780 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5781 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5782 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5783 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5784 ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s16>)5785 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF5786 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[DEF]](s16)5787 ; CHECK-NEXT: [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s16>)5788 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)5789 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)5790 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5791 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)5792 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](s32)5793 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5794 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35795 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5796 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5797 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5798 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5799 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5800 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5801 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5802 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5803 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5804 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5805 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v3f16_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315806 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5807 ; CHECK-NEXT: SI_RETURN5808 call void @external_void_func_v3f16_inreg(<3 x half> inreg %arg)5809 ret void5810}5811 5812define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0 {5813 ; CHECK-LABEL: name: test_call_external_void_func_v4f16_inreg5814 ; CHECK: bb.1 (%ir-block.0):5815 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115816 ; CHECK-NEXT: {{ $}}5817 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315818 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155819 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145820 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135821 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125822 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115823 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95824 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75825 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55826 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(<2 x s16>) = COPY $sgpr165827 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(<2 x s16>) = COPY $sgpr175828 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[COPY9]](<2 x s16>), [[COPY10]](<2 x s16>)5829 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5830 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v4f16_inreg5831 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5832 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5833 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5834 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5835 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5836 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5837 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5838 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5839 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5840 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s16>)5841 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)5842 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32)5843 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5844 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)5845 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](s32)5846 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5847 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35848 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5849 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5850 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5851 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5852 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5853 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5854 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5855 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5856 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5857 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5858 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v4f16_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315859 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5860 ; CHECK-NEXT: SI_RETURN5861 call void @external_void_func_v4f16_inreg(<4 x half> inreg %arg)5862 ret void5863}5864 5865define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 {5866 ; CHECK-LABEL: name: test_call_external_void_func_p0_inreg5867 ; CHECK: bb.1 (%ir-block.0):5868 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115869 ; CHECK-NEXT: {{ $}}5870 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315871 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155872 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145873 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135874 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125875 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115876 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95877 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75878 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55879 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165880 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr175881 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)5882 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5883 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_p0_inreg5884 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5885 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5886 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5887 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5888 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5889 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5890 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5891 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5892 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5893 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p0)5894 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)5895 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5896 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)5897 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5898 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35899 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5900 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5901 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5902 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5903 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5904 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5905 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5906 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5907 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5908 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5909 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p0_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315910 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5911 ; CHECK-NEXT: SI_RETURN5912 call void @external_void_func_p0_inreg(ptr inreg %arg)5913 ret void5914}5915 5916define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg) #0 {5917 ; CHECK-LABEL: name: test_call_external_void_func_p1_inreg5918 ; CHECK: bb.1 (%ir-block.0):5919 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115920 ; CHECK-NEXT: {{ $}}5921 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315922 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155923 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145924 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135925 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125926 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115927 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95928 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75929 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55930 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr165931 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr175932 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)5933 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5934 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_p1_inreg5935 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]5936 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]5937 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]5938 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]5939 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]5940 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]5941 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]5942 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]5943 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5944 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p1)5945 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)5946 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5947 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)5948 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)5949 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35950 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)5951 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)5952 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)5953 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)5954 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)5955 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)5956 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)5957 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)5958 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)5959 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)5960 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p1_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr315961 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc5962 ; CHECK-NEXT: SI_RETURN5963 call void @external_void_func_p1_inreg(ptr addrspace(1) inreg %arg)5964 ret void5965}5966 5967define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg) #0 {5968 ; CHECK-LABEL: name: test_call_external_void_func_p3_inreg5969 ; CHECK: bb.1 (%ir-block.0):5970 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr115971 ; CHECK-NEXT: {{ $}}5972 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr315973 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr155974 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr145975 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr135976 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr125977 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr115978 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr95979 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr75980 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr55981 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p3) = COPY $sgpr165982 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc5983 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_p3_inreg5984 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY8]]5985 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY7]]5986 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY6]]5987 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY5]]5988 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]]5989 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]]5990 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]]5991 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]]5992 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)5993 ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY9]](p3)5994 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32)5995 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)5996 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr35997 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)5998 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4)5999 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY11]](p4)6000 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY12]](p4)6001 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY13]](s64)6002 ; CHECK-NEXT: $sgpr12 = COPY [[COPY14]](s32)6003 ; CHECK-NEXT: $sgpr13 = COPY [[COPY15]](s32)6004 ; CHECK-NEXT: $sgpr14 = COPY [[COPY16]](s32)6005 ; CHECK-NEXT: $sgpr15 = COPY [[COPY17]](s32)6006 ; CHECK-NEXT: $vgpr31 = COPY [[COPY18]](s32)6007 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_p3_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr316008 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc6009 ; CHECK-NEXT: SI_RETURN6010 call void @external_void_func_p3_inreg(ptr addrspace(3) inreg %arg)6011 ret void6012}6013 6014define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inreg %arg) #0 {6015 ; CHECK-LABEL: name: test_call_external_void_func_v2p1_inreg6016 ; CHECK: bb.1 (%ir-block.0):6017 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $sgpr18, $sgpr19, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr116018 ; CHECK-NEXT: {{ $}}6019 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr316020 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr156021 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr146022 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr136023 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr126024 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr116025 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr96026 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr76027 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr56028 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr166029 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr176030 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr186031 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(s32) = COPY $sgpr196032 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)6033 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY11]](s32), [[COPY12]](s32)6034 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p1>) = G_BUILD_VECTOR [[MV]](p1), [[MV1]](p1)6035 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc6036 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2p1_inreg6037 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY8]]6038 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(p4) = COPY [[COPY7]]6039 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(p4) = COPY [[COPY6]]6040 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s64) = COPY [[COPY5]]6041 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY4]]6042 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY3]]6043 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY2]]6044 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY1]]6045 ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)6046 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x p1>)6047 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)6048 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)6049 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)6050 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)6051 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32)6052 ; CHECK-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32)6053 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV3]](s32)6054 ; CHECK-NEXT: $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](s32)6055 ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr36056 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>)6057 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY13]](p4)6058 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY14]](p4)6059 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY15]](p4)6060 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY16]](s64)6061 ; CHECK-NEXT: $sgpr12 = COPY [[COPY17]](s32)6062 ; CHECK-NEXT: $sgpr13 = COPY [[COPY18]](s32)6063 ; CHECK-NEXT: $sgpr14 = COPY [[COPY19]](s32)6064 ; CHECK-NEXT: $sgpr15 = COPY [[COPY20]](s32)6065 ; CHECK-NEXT: $vgpr31 = COPY [[COPY21]](s32)6066 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2p1_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $sgpr3, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr316067 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc6068 ; CHECK-NEXT: SI_RETURN6069 call void @external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inreg %arg)6070 ret void6071}6072 6073define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inreg %arg) #0 {6074 ; CHECK-LABEL: name: test_call_external_void_func_v2p5_inreg6075 ; CHECK: bb.1 (%ir-block.0):6076 ; CHECK-NEXT: liveins: $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr116077 ; CHECK-NEXT: {{ $}}6078 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr316079 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr156080 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr146081 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr136082 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr126083 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr116084 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr96085 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr76086 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr56087 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:_(p5) = COPY $sgpr166088 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:_(p5) = COPY $sgpr176089 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p5>) = G_BUILD_VECTOR [[COPY9]](p5), [[COPY10]](p5)6090 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc6091 ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_void_func_v2p5_inreg6092 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]6093 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]6094 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY6]]6095 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY5]]6096 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY4]]6097 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY3]]6098 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY2]]6099 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]]6100 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)6101 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x p5>)6102 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32)6103 ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32)6104 ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)6105 ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)6106 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr36107 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)6108 ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4)6109 ; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY12]](p4)6110 ; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY13]](p4)6111 ; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY14]](s64)6112 ; CHECK-NEXT: $sgpr12 = COPY [[COPY15]](s32)6113 ; CHECK-NEXT: $sgpr13 = COPY [[COPY16]](s32)6114 ; CHECK-NEXT: $sgpr14 = COPY [[COPY17]](s32)6115 ; CHECK-NEXT: $sgpr15 = COPY [[COPY18]](s32)6116 ; CHECK-NEXT: $vgpr31 = COPY [[COPY19]](s32)6117 ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_void_func_v2p5_inreg, csr_amdgpu, implicit $sgpr0, implicit $sgpr1, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr316118 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $scc6119 ; CHECK-NEXT: SI_RETURN6120 call void @external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inreg %arg)6121 ret void6122}6123 6124attributes #0 = { nounwind }6125attributes #1 = { nounwind readnone }6126attributes #2 = { nounwind noinline }6127 6128