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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s3 4define amdgpu_kernel void @asm_convergent() convergent{5 ; CHECK-LABEL: name: asm_convergent6 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $sgpr8_sgpr98 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr910 ; CHECK-NEXT: INLINEASM &s_barrier, 33 /* sideeffect isconvergent attdialect */, !111 ; CHECK-NEXT: S_ENDPGM 012 call void asm sideeffect "s_barrier", ""() convergent, !srcloc !013 ret void14}15 16define amdgpu_kernel void @asm_simple_memory_clobber() {17 ; CHECK-LABEL: name: asm_simple_memory_clobber18 ; CHECK: bb.1 (%ir-block.0):19 ; CHECK-NEXT: liveins: $sgpr8_sgpr920 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr922 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, !123 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, !124 ; CHECK-NEXT: S_ENDPGM 025 call void asm sideeffect "", "~{memory}"(), !srcloc !026 call void asm sideeffect "", ""(), !srcloc !027 ret void28}29 30define amdgpu_kernel void @asm_simple_vgpr_clobber() {31 ; CHECK-LABEL: name: asm_simple_vgpr_clobber32 ; CHECK: bb.1 (%ir-block.0):33 ; CHECK-NEXT: liveins: $sgpr8_sgpr934 ; CHECK-NEXT: {{ $}}35 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr936 ; CHECK-NEXT: INLINEASM &"v_mov_b32 v0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0, !137 ; CHECK-NEXT: S_ENDPGM 038 call void asm sideeffect "v_mov_b32 v0, 7", "~{v0}"(), !srcloc !039 ret void40}41 42define amdgpu_kernel void @asm_simple_sgpr_clobber() {43 ; CHECK-LABEL: name: asm_simple_sgpr_clobber44 ; CHECK: bb.1 (%ir-block.0):45 ; CHECK-NEXT: liveins: $sgpr8_sgpr946 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr948 ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, 7", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $sgpr0, !149 ; CHECK-NEXT: S_ENDPGM 050 call void asm sideeffect "s_mov_b32 s0, 7", "~{s0}"(), !srcloc !051 ret void52}53 54define amdgpu_kernel void @asm_simple_agpr_clobber() {55 ; CHECK-LABEL: name: asm_simple_agpr_clobber56 ; CHECK: bb.1 (%ir-block.0):57 ; CHECK-NEXT: liveins: $sgpr8_sgpr958 ; CHECK-NEXT: {{ $}}59 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr960 ; CHECK-NEXT: INLINEASM &"; def a0", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $agpr0, !161 ; CHECK-NEXT: S_ENDPGM 062 call void asm sideeffect "; def a0", "~{a0}"(), !srcloc !063 ret void64}65 66define i32 @asm_vgpr_early_clobber() {67 ; CHECK-LABEL: name: asm_vgpr_early_clobber68 ; CHECK: bb.1 (%ir-block.0):69 ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7; v_mov_b32 $1, 7", 1 /* sideeffect attdialect */, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %8, 1245195 /* regdef-ec:VGPR_32 */, def early-clobber %9, !170 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %871 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %972 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]73 ; CHECK-NEXT: $vgpr0 = COPY [[ADD]](s32)74 ; CHECK-NEXT: SI_RETURN implicit $vgpr075 call { i32, i32 } asm sideeffect "v_mov_b32 $0, 7; v_mov_b32 $1, 7", "=&v,=&v"(), !srcloc !076 %asmresult = extractvalue { i32, i32 } %1, 077 %asmresult1 = extractvalue { i32, i32 } %1, 178 %add = add i32 %asmresult, %asmresult179 ret i32 %add80}81 82define i32 @test_specific_vgpr_output() nounwind {83 ; CHECK-LABEL: name: test_specific_vgpr_output84 ; CHECK: bb.1.entry:85 ; CHECK-NEXT: INLINEASM &"v_mov_b32 v1, 7", 0 /* attdialect */, 10 /* regdef */, implicit-def $vgpr186 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr187 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)88 ; CHECK-NEXT: SI_RETURN implicit $vgpr089entry:90 %0 = tail call i32 asm "v_mov_b32 v1, 7", "={v1}"() nounwind91 ret i32 %092}93 94define i32 @test_single_vgpr_output() nounwind {95 ; CHECK-LABEL: name: test_single_vgpr_output96 ; CHECK: bb.1.entry:97 ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 7", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %898 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %899 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)100 ; CHECK-NEXT: SI_RETURN implicit $vgpr0101entry:102 %0 = tail call i32 asm "v_mov_b32 $0, 7", "=v"() nounwind103 ret i32 %0104}105 106define i32 @test_single_sgpr_output_s32() nounwind {107 ; CHECK-LABEL: name: test_single_sgpr_output_s32108 ; CHECK: bb.1.entry:109 ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %8110 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8111 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)112 ; CHECK-NEXT: SI_RETURN implicit $vgpr0113entry:114 %0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind115 ret i32 %0116}117 118; Check support for returning several floats119define float @test_multiple_register_outputs_same() #0 {120 ; CHECK-LABEL: name: test_multiple_register_outputs_same121 ; CHECK: bb.1 (%ir-block.0):122 ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_mov_b32 $1, 1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %8, 1245194 /* regdef:VGPR_32 */, def %9123 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8124 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9125 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]]126 ; CHECK-NEXT: $vgpr0 = COPY [[FADD]](s32)127 ; CHECK-NEXT: SI_RETURN implicit $vgpr0128 %1 = call { float, float } asm "v_mov_b32 $0, 0; v_mov_b32 $1, 1", "=v,=v"()129 %asmresult = extractvalue { float, float } %1, 0130 %asmresult1 = extractvalue { float, float } %1, 1131 %add = fadd float %asmresult, %asmresult1132 ret float %add133}134 135; Check support for returning several floats136define double @test_multiple_register_outputs_mixed() #0 {137 ; CHECK-LABEL: name: test_multiple_register_outputs_mixed138 ; CHECK: bb.1 (%ir-block.0):139 ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %8, 2818058 /* regdef:VReg_64 */, def %9140 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8141 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY %9142 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)143 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)144 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)145 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1146 %1 = call { float, double } asm "v_mov_b32 $0, 0; v_add_f64 $1, 0, 0", "=v,=v"()147 %asmresult = extractvalue { float, double } %1, 1148 ret double %asmresult149}150 151 152define float @test_vector_output() nounwind {153 ; CHECK-LABEL: name: test_vector_output154 ; CHECK: bb.1 (%ir-block.0):155 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0156 ; CHECK-NEXT: INLINEASM &"v_add_f64 $0, 0, 0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr14_vgpr15157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr14_vgpr15158 ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)159 ; CHECK-NEXT: $vgpr0 = COPY [[EVEC]](s32)160 ; CHECK-NEXT: SI_RETURN implicit $vgpr0161 %1 = tail call <2 x float> asm sideeffect "v_add_f64 $0, 0, 0", "={v[14:15]}"() nounwind162 %2 = extractelement <2 x float> %1, i32 0163 ret float %2164}165 166define amdgpu_kernel void @test_input_vgpr_imm() {167 ; CHECK-LABEL: name: test_input_vgpr_imm168 ; CHECK: bb.1 (%ir-block.0):169 ; CHECK-NEXT: liveins: $sgpr8_sgpr9170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9172 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42173 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[C]](s32)174 ; CHECK-NEXT: INLINEASM &"v_mov_b32 v0, $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY1]]175 ; CHECK-NEXT: S_ENDPGM 0176 call void asm sideeffect "v_mov_b32 v0, $0", "v"(i32 42)177 ret void178}179 180define amdgpu_kernel void @test_input_sgpr_imm() {181 ; CHECK-LABEL: name: test_input_sgpr_imm182 ; CHECK: bb.1 (%ir-block.0):183 ; CHECK-NEXT: liveins: $sgpr8_sgpr9184 ; CHECK-NEXT: {{ $}}185 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9186 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42187 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[C]](s32)188 ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, $0", 1 /* sideeffect attdialect */, 1835017 /* reguse:SReg_32 */, [[COPY1]]189 ; CHECK-NEXT: S_ENDPGM 0190 call void asm sideeffect "s_mov_b32 s0, $0", "s"(i32 42)191 ret void192}193 194define amdgpu_kernel void @test_input_imm() {195 ; CHECK-LABEL: name: test_input_imm196 ; CHECK: bb.1 (%ir-block.0):197 ; CHECK-NEXT: liveins: $sgpr8_sgpr9198 ; CHECK-NEXT: {{ $}}199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9200 ; CHECK-NEXT: INLINEASM &"s_mov_b32 s0, $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42201 ; CHECK-NEXT: INLINEASM &"s_mov_b64 s[0:1], $0", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 42202 ; CHECK-NEXT: S_ENDPGM 0203 call void asm sideeffect "s_mov_b32 s0, $0", "i"(i32 42)204 call void asm sideeffect "s_mov_b64 s[0:1], $0", "i"(i64 42)205 ret void206}207 208define float @test_input_vgpr(i32 %src) nounwind {209 ; CHECK-LABEL: name: test_input_vgpr210 ; CHECK: bb.1.entry:211 ; CHECK-NEXT: liveins: $vgpr0212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0214 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)215 ; CHECK-NEXT: INLINEASM &"v_add_f32 $0, 1.0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %9, 1245193 /* reguse:VGPR_32 */, [[COPY1]]216 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %9217 ; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)218 ; CHECK-NEXT: SI_RETURN implicit $vgpr0219entry:220 %0 = tail call float asm "v_add_f32 $0, 1.0, $1", "=v,v"(i32 %src) nounwind221 ret float %0222}223 224define i32 @test_memory_constraint(ptr addrspace(3) %a) nounwind {225 ; CHECK-LABEL: name: test_memory_constraint226 ; CHECK: bb.1 (%ir-block.0):227 ; CHECK-NEXT: liveins: $vgpr0228 ; CHECK-NEXT: {{ $}}229 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0230 ; CHECK-NEXT: INLINEASM &"ds_read_b32 $0, $1", 8 /* mayload attdialect */, 1245194 /* regdef:VGPR_32 */, def %9, 262158 /* mem:m */, [[COPY]](p3)231 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %9232 ; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)233 ; CHECK-NEXT: SI_RETURN implicit $vgpr0234 %1 = tail call i32 asm "ds_read_b32 $0, $1", "=v,*m"(ptr addrspace(3) elementtype(i32) %a)235 ret i32 %1236}237 238define i32 @test_vgpr_matching_constraint(i32 %a) nounwind {239 ; CHECK-LABEL: name: test_vgpr_matching_constraint240 ; CHECK: bb.1 (%ir-block.0):241 ; CHECK-NEXT: liveins: $vgpr0242 ; CHECK-NEXT: {{ $}}243 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0244 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1245 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]246 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AND]](s32)247 ; CHECK-NEXT: INLINEASM &";", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %11, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)248 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %11249 ; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)250 ; CHECK-NEXT: SI_RETURN implicit $vgpr0251 %and = and i32 %a, 1252 %asm = call i32 asm sideeffect ";", "=v,0"(i32 %and)253 ret i32 %asm254}255 256define i32 @test_sgpr_matching_constraint() nounwind {257 ; CHECK-LABEL: name: test_sgpr_matching_constraint258 ; CHECK: bb.1.entry:259 ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %8260 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8261 ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 8", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %10262 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY %10263 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]](s32)264 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]](s32)265 ; CHECK-NEXT: INLINEASM &"s_add_u32 $0, $1, $2", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %12, 1835017 /* reguse:SReg_32 */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)266 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY %12267 ; CHECK-NEXT: $vgpr0 = COPY [[COPY4]](s32)268 ; CHECK-NEXT: SI_RETURN implicit $vgpr0269entry:270 %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind271 %asm1 = tail call i32 asm "s_mov_b32 $0, 8", "=s"() nounwind272 %asm2 = tail call i32 asm "s_add_u32 $0, $1, $2", "=s,s,0"(i32 %asm0, i32 %asm1) nounwind273 ret i32 %asm2274}275 276define void @test_many_matching_constraints(i32 %a, i32 %b, i32 %c) nounwind {277 ; CHECK-LABEL: name: test_many_matching_constraints278 ; CHECK: bb.1 (%ir-block.0):279 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2280 ; CHECK-NEXT: {{ $}}281 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0282 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1283 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2284 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF285 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]](s32)286 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)287 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]](s32)288 ; CHECK-NEXT: INLINEASM &"; ", 1 /* sideeffect attdialect */, 1245194 /* regdef:VGPR_32 */, def %11, 1245194 /* regdef:VGPR_32 */, def %12, 1245194 /* regdef:VGPR_32 */, def %13, 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3), 2147614729 /* reguse tiedto:$2 */, [[COPY4]](tied-def 7), 2147549193 /* reguse tiedto:$1 */, [[COPY5]](tied-def 5)289 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY %11290 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY %12291 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY %13292 ; CHECK-NEXT: G_STORE [[COPY6]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)293 ; CHECK-NEXT: G_STORE [[COPY7]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)294 ; CHECK-NEXT: G_STORE [[COPY8]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)295 ; CHECK-NEXT: SI_RETURN296 %asm = call {i32, i32, i32} asm sideeffect "; ", "=v,=v,=v,0,2,1"(i32 %c, i32 %a, i32 %b)297 %asmresult0 = extractvalue {i32, i32, i32} %asm, 0298 store i32 %asmresult0, ptr addrspace(1) poison299 %asmresult1 = extractvalue {i32, i32, i32} %asm, 1300 store i32 %asmresult1, ptr addrspace(1) poison301 %asmresult2 = extractvalue {i32, i32, i32} %asm, 2302 store i32 %asmresult2, ptr addrspace(1) poison303 ret void304}305 306define i32 @test_sgpr_to_vgpr_move_matching_constraint() nounwind {307 ; CHECK-LABEL: name: test_sgpr_to_vgpr_move_matching_constraint308 ; CHECK: bb.1.entry:309 ; CHECK-NEXT: INLINEASM &"s_mov_b32 $0, 7", 0 /* attdialect */, 1835018 /* regdef:SReg_32 */, def %8310 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY %8311 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]](s32)312 ; CHECK-NEXT: INLINEASM &"v_mov_b32 $0, $1", 0 /* attdialect */, 1245194 /* regdef:VGPR_32 */, def %10, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)313 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY %10314 ; CHECK-NEXT: $vgpr0 = COPY [[COPY2]](s32)315 ; CHECK-NEXT: SI_RETURN implicit $vgpr0316entry:317 %asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind318 %asm1 = tail call i32 asm "v_mov_b32 $0, $1", "=v,0"(i32 %asm0) nounwind319 ret i32 %asm1320}321 322define amdgpu_kernel void @asm_constraint_n_n() {323 ; CHECK-LABEL: name: asm_constraint_n_n324 ; CHECK: bb.1 (%ir-block.0):325 ; CHECK-NEXT: liveins: $sgpr8_sgpr9326 ; CHECK-NEXT: {{ $}}327 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9328 ; CHECK-NEXT: INLINEASM &"s_trap ${0:n}", 1 /* sideeffect attdialect */, 13 /* imm */, 10329 ; CHECK-NEXT: S_ENDPGM 0330 tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1331 ret void332}333 334define void @test_indirectify_i32_value(i32 %x, i32 %y) {335 ; CHECK-LABEL: name: test_indirectify_i32_value336 ; CHECK: bb.1.entry:337 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1338 ; CHECK-NEXT: {{ $}}339 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0340 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1341 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0342 ; CHECK-NEXT: G_STORE [[COPY]](s32), [[FRAME_INDEX]](p5) :: (store (s32) into %stack.0, addrspace 5)343 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.1344 ; CHECK-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX1]](p5) :: (store (s32) into %stack.1, addrspace 5)345 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p5), 262158 /* mem:m */, [[FRAME_INDEX1]](p5)346 ; CHECK-NEXT: SI_RETURN347entry:348 tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)349 ret void350}351 352define void @test_indirectify_i32_constant() {353 ; CHECK-LABEL: name: test_indirectify_i32_constant354 ; CHECK: bb.1.entry:355 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42356 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0357 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0358 ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p5) :: (store (s32) into %stack.0, addrspace 5)359 ; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.1360 ; CHECK-NEXT: G_STORE [[C1]](s32), [[FRAME_INDEX1]](p5) :: (store (s32) into %stack.1, addrspace 5)361 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p5), 262158 /* mem:m */, [[FRAME_INDEX1]](p5)362 ; CHECK-NEXT: SI_RETURN363entry:364 tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 42, i32 0)365 ret void366}367 368 369define void @test_indirectify_i16_value(i16 %val) {370 ; CHECK-LABEL: name: test_indirectify_i16_value371 ; CHECK: bb.1.entry:372 ; CHECK-NEXT: liveins: $vgpr0373 ; CHECK-NEXT: {{ $}}374 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0375 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)376 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0377 ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[FRAME_INDEX]](p5) :: (store (s16) into %stack.0, addrspace 5)378 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p5)379 ; CHECK-NEXT: SI_RETURN380entry:381 tail call void asm sideeffect "", "imr,~{memory}"(i16 %val)382 ret void383}384 385define void @test_indirectify_i16_constant() {386 ; CHECK-LABEL: name: test_indirectify_i16_constant387 ; CHECK: bb.1.entry:388 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 42389 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0390 ; CHECK-NEXT: G_STORE [[C]](s16), [[FRAME_INDEX]](p5) :: (store (s16) into %stack.0, addrspace 5)391 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p5)392 ; CHECK-NEXT: SI_RETURN393entry:394 tail call void asm sideeffect "", "imr,~{memory}"(i16 42)395 ret void396}397 398define void @test_indirectify_i64_value(i64 %val) {399 ; CHECK-LABEL: name: test_indirectify_i64_value400 ; CHECK: bb.1.entry:401 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1402 ; CHECK-NEXT: {{ $}}403 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0404 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1405 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)406 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0407 ; CHECK-NEXT: G_STORE [[MV]](s64), [[FRAME_INDEX]](p5) :: (store (s64) into %stack.0, addrspace 5)408 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p5)409 ; CHECK-NEXT: SI_RETURN410entry:411 tail call void asm sideeffect "", "imr,~{memory}"(i64 %val)412 ret void413}414 415define void @test_indirectify_i64_constant() {416 ; CHECK-LABEL: name: test_indirectify_i64_constant417 ; CHECK: bb.1.entry:418 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 42419 ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0420 ; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p5) :: (store (s64) into %stack.0, addrspace 5)421 ; CHECK-NEXT: INLINEASM &"", 25 /* sideeffect mayload maystore attdialect */, 262158 /* mem:m */, [[FRAME_INDEX]](p5)422 ; CHECK-NEXT: SI_RETURN423entry:424 tail call void asm sideeffect "", "imr,~{memory}"(i64 42)425 ret void426}427 428!llvm.module.flags = !{!1}429!0 = !{i32 70}430!1 = !{i32 1, !"amdhsa_code_object_version", i32 500}431