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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=amdgcn -global-isel -stop-after=irtranslator %s -o - | FileCheck %s3 4define i16 @uaddsat_i16(i16 %lhs, i16 %rhs) {5 ; CHECK-LABEL: name: uaddsat_i166 ; CHECK: bb.1 (%ir-block.0):7 ; CHECK-NEXT: liveins: $vgpr0, $vgpr18 ; CHECK-NEXT: {{ $}}9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr010 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr112 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)13 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]14 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)15 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)16 ; CHECK-NEXT: SI_RETURN implicit $vgpr017 %res = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)18 ret i16 %res19}20declare i16 @llvm.uadd.sat.i16(i16, i16)21 22define i32 @uaddsat_i32(i32 %lhs, i32 %rhs) {23 ; CHECK-LABEL: name: uaddsat_i3224 ; CHECK: bb.1 (%ir-block.0):25 ; CHECK-NEXT: liveins: $vgpr0, $vgpr126 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr028 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr129 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]30 ; CHECK-NEXT: $vgpr0 = COPY [[UADDSAT]](s32)31 ; CHECK-NEXT: SI_RETURN implicit $vgpr032 %res = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)33 ret i32 %res34}35declare i32 @llvm.uadd.sat.i32(i32, i32)36 37define i64 @uaddsat_i64(i64 %lhs, i64 %rhs) {38 ; CHECK-LABEL: name: uaddsat_i6439 ; CHECK: bb.1 (%ir-block.0):40 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr341 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr043 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr144 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)45 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr246 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr347 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)48 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(s64) = G_UADDSAT [[MV]], [[MV1]]49 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](s64)50 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)51 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)52 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr153 %res = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)54 ret i64 %res55}56declare i64 @llvm.uadd.sat.i64(i64, i64)57 58define <2 x i32> @uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {59 ; CHECK-LABEL: name: uaddsat_v2i3260 ; CHECK: bb.1 (%ir-block.0):61 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr362 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr064 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr165 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)66 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr267 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr368 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)69 ; CHECK-NEXT: [[UADDSAT:%[0-9]+]]:_(<2 x s32>) = G_UADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]70 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UADDSAT]](<2 x s32>)71 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)72 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)73 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr174 %res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)75 ret <2 x i32> %res76}77declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)78 79define i16 @saddsat_i16(i16 %lhs, i16 %rhs) {80 ; CHECK-LABEL: name: saddsat_i1681 ; CHECK: bb.1 (%ir-block.0):82 ; CHECK-NEXT: liveins: $vgpr0, $vgpr183 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr085 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)86 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr187 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)88 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]89 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)90 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)91 ; CHECK-NEXT: SI_RETURN implicit $vgpr092 %res = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)93 ret i16 %res94}95declare i16 @llvm.sadd.sat.i16(i16, i16)96 97define i32 @saddsat_i32(i32 %lhs, i32 %rhs) {98 ; CHECK-LABEL: name: saddsat_i3299 ; CHECK: bb.1 (%ir-block.0):100 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1101 ; CHECK-NEXT: {{ $}}102 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0103 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1104 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]]105 ; CHECK-NEXT: $vgpr0 = COPY [[SADDSAT]](s32)106 ; CHECK-NEXT: SI_RETURN implicit $vgpr0107 %res = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)108 ret i32 %res109}110declare i32 @llvm.sadd.sat.i32(i32, i32)111 112define i64 @saddsat_i64(i64 %lhs, i64 %rhs) {113 ; CHECK-LABEL: name: saddsat_i64114 ; CHECK: bb.1 (%ir-block.0):115 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1119 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)120 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2121 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3122 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)123 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(s64) = G_SADDSAT [[MV]], [[MV1]]124 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](s64)125 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)126 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)127 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1128 %res = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)129 ret i64 %res130}131declare i64 @llvm.sadd.sat.i64(i64, i64)132 133define <2 x i32> @saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {134 ; CHECK-LABEL: name: saddsat_v2i32135 ; CHECK: bb.1 (%ir-block.0):136 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0139 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1140 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)141 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2142 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3143 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)144 ; CHECK-NEXT: [[SADDSAT:%[0-9]+]]:_(<2 x s32>) = G_SADDSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]145 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SADDSAT]](<2 x s32>)146 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)147 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)148 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1149 %res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)150 ret <2 x i32> %res151}152declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)153 154define i16 @usubsat_i16(i16 %lhs, i16 %rhs) {155 ; CHECK-LABEL: name: usubsat_i16156 ; CHECK: bb.1 (%ir-block.0):157 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1158 ; CHECK-NEXT: {{ $}}159 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0160 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)161 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1162 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)163 ; CHECK-NEXT: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]164 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)165 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)166 ; CHECK-NEXT: SI_RETURN implicit $vgpr0167 %res = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)168 ret i16 %res169}170declare i16 @llvm.usub.sat.i16(i16, i16)171 172define i32 @usubsat_i32(i32 %lhs, i32 %rhs) {173 ; CHECK-LABEL: name: usubsat_i32174 ; CHECK: bb.1 (%ir-block.0):175 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1176 ; CHECK-NEXT: {{ $}}177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1179 ; CHECK-NEXT: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]180 ; CHECK-NEXT: $vgpr0 = COPY [[USUBSAT]](s32)181 ; CHECK-NEXT: SI_RETURN implicit $vgpr0182 %res = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)183 ret i32 %res184}185declare i32 @llvm.usub.sat.i32(i32, i32)186 187define i64 @usubsat_i64(i64 %lhs, i64 %rhs) {188 ; CHECK-LABEL: name: usubsat_i64189 ; CHECK: bb.1 (%ir-block.0):190 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3191 ; CHECK-NEXT: {{ $}}192 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0193 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1194 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)195 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2196 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3197 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)198 ; CHECK-NEXT: [[USUBSAT:%[0-9]+]]:_(s64) = G_USUBSAT [[MV]], [[MV1]]199 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](s64)200 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)201 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)202 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1203 %res = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)204 ret i64 %res205}206declare i64 @llvm.usub.sat.i64(i64, i64)207 208define <2 x i32> @usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {209 ; CHECK-LABEL: name: usubsat_v2i32210 ; CHECK: bb.1 (%ir-block.0):211 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0214 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1215 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)216 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2217 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3218 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)219 ; CHECK-NEXT: [[USUBSAT:%[0-9]+]]:_(<2 x s32>) = G_USUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]220 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USUBSAT]](<2 x s32>)221 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)222 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)223 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1224 %res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)225 ret <2 x i32> %res226}227declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>)228 229define i16 @ssubsat_i16(i16 %lhs, i16 %rhs) {230 ; CHECK-LABEL: name: ssubsat_i16231 ; CHECK: bb.1 (%ir-block.0):232 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1233 ; CHECK-NEXT: {{ $}}234 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0235 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)236 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1237 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)238 ; CHECK-NEXT: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[TRUNC]], [[TRUNC1]]239 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBSAT]](s16)240 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)241 ; CHECK-NEXT: SI_RETURN implicit $vgpr0242 %res = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)243 ret i16 %res244}245declare i16 @llvm.ssub.sat.i16(i16, i16)246 247define i32 @ssubsat_i32(i32 %lhs, i32 %rhs) {248 ; CHECK-LABEL: name: ssubsat_i32249 ; CHECK: bb.1 (%ir-block.0):250 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1251 ; CHECK-NEXT: {{ $}}252 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0253 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1254 ; CHECK-NEXT: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[COPY]], [[COPY1]]255 ; CHECK-NEXT: $vgpr0 = COPY [[SSUBSAT]](s32)256 ; CHECK-NEXT: SI_RETURN implicit $vgpr0257 %res = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)258 ret i32 %res259}260declare i32 @llvm.ssub.sat.i32(i32, i32)261 262define i64 @ssubsat_i64(i64 %lhs, i64 %rhs) {263 ; CHECK-LABEL: name: ssubsat_i64264 ; CHECK: bb.1 (%ir-block.0):265 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3266 ; CHECK-NEXT: {{ $}}267 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0268 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1269 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)270 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2271 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3272 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)273 ; CHECK-NEXT: [[SSUBSAT:%[0-9]+]]:_(s64) = G_SSUBSAT [[MV]], [[MV1]]274 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](s64)275 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)276 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)277 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1278 %res = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)279 ret i64 %res280}281declare i64 @llvm.ssub.sat.i64(i64, i64)282 283define <2 x i32> @ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {284 ; CHECK-LABEL: name: ssubsat_v2i32285 ; CHECK: bb.1 (%ir-block.0):286 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3287 ; CHECK-NEXT: {{ $}}288 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0289 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1290 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)291 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2292 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3293 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)294 ; CHECK-NEXT: [[SSUBSAT:%[0-9]+]]:_(<2 x s32>) = G_SSUBSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]]295 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSUBSAT]](<2 x s32>)296 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)297 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)298 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1299 %res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)300 ret <2 x i32> %res301}302declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)303 304define i16 @ushlsat_i16(i16 %lhs, i16 %rhs) {305 ; CHECK-LABEL: name: ushlsat_i16306 ; CHECK: bb.1 (%ir-block.0):307 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1308 ; CHECK-NEXT: {{ $}}309 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0310 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)311 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1312 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)313 ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s16) = G_USHLSAT [[TRUNC]], [[TRUNC1]](s16)314 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USHLSAT]](s16)315 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)316 ; CHECK-NEXT: SI_RETURN implicit $vgpr0317 %res = call i16 @llvm.ushl.sat.i16(i16 %lhs, i16 %rhs)318 ret i16 %res319}320declare i16 @llvm.ushl.sat.i16(i16, i16)321 322define i32 @ushlsat_i32(i32 %lhs, i32 %rhs) {323 ; CHECK-LABEL: name: ushlsat_i32324 ; CHECK: bb.1 (%ir-block.0):325 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1326 ; CHECK-NEXT: {{ $}}327 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0328 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1329 ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[COPY1]](s32)330 ; CHECK-NEXT: $vgpr0 = COPY [[USHLSAT]](s32)331 ; CHECK-NEXT: SI_RETURN implicit $vgpr0332 %res = call i32 @llvm.ushl.sat.i32(i32 %lhs, i32 %rhs)333 ret i32 %res334}335declare i32 @llvm.ushl.sat.i32(i32, i32)336 337define i64 @ushlsat_i64(i64 %lhs, i64 %rhs) {338 ; CHECK-LABEL: name: ushlsat_i64339 ; CHECK: bb.1 (%ir-block.0):340 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3341 ; CHECK-NEXT: {{ $}}342 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0343 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1344 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)345 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2346 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3347 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)348 ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[MV1]](s64)349 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](s64)350 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)351 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)352 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1353 %res = call i64 @llvm.ushl.sat.i64(i64 %lhs, i64 %rhs)354 ret i64 %res355}356declare i64 @llvm.ushl.sat.i64(i64, i64)357 358define <2 x i32> @ushlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {359 ; CHECK-LABEL: name: ushlsat_v2i32360 ; CHECK: bb.1 (%ir-block.0):361 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3362 ; CHECK-NEXT: {{ $}}363 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0364 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1365 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)366 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2367 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3368 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)369 ; CHECK-NEXT: [[USHLSAT:%[0-9]+]]:_(<2 x s32>) = G_USHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>)370 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](<2 x s32>)371 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)372 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)373 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1374 %res = call <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)375 ret <2 x i32> %res376}377declare <2 x i32> @llvm.ushl.sat.v2i32(<2 x i32>, <2 x i32>)378 379define i16 @sshlsat_i16(i16 %lhs, i16 %rhs) {380 ; CHECK-LABEL: name: sshlsat_i16381 ; CHECK: bb.1 (%ir-block.0):382 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1383 ; CHECK-NEXT: {{ $}}384 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0385 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)386 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1387 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)388 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s16) = G_SSHLSAT [[TRUNC]], [[TRUNC1]](s16)389 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSHLSAT]](s16)390 ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)391 ; CHECK-NEXT: SI_RETURN implicit $vgpr0392 %res = call i16 @llvm.sshl.sat.i16(i16 %lhs, i16 %rhs)393 ret i16 %res394}395declare i16 @llvm.sshl.sat.i16(i16, i16)396 397define i32 @sshlsat_i32(i32 %lhs, i32 %rhs) {398 ; CHECK-LABEL: name: sshlsat_i32399 ; CHECK: bb.1 (%ir-block.0):400 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1401 ; CHECK-NEXT: {{ $}}402 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0403 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1404 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[COPY1]](s32)405 ; CHECK-NEXT: $vgpr0 = COPY [[SSHLSAT]](s32)406 ; CHECK-NEXT: SI_RETURN implicit $vgpr0407 %res = call i32 @llvm.sshl.sat.i32(i32 %lhs, i32 %rhs)408 ret i32 %res409}410declare i32 @llvm.sshl.sat.i32(i32, i32)411 412define i64 @sshlsat_i64(i64 %lhs, i64 %rhs) {413 ; CHECK-LABEL: name: sshlsat_i64414 ; CHECK: bb.1 (%ir-block.0):415 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3416 ; CHECK-NEXT: {{ $}}417 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0418 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1419 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)420 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2421 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3422 ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)423 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(s64) = G_SSHLSAT [[MV]], [[MV1]](s64)424 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](s64)425 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)426 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)427 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1428 %res = call i64 @llvm.sshl.sat.i64(i64 %lhs, i64 %rhs)429 ret i64 %res430}431declare i64 @llvm.sshl.sat.i64(i64, i64)432 433define <2 x i32> @sshlsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {434 ; CHECK-LABEL: name: sshlsat_v2i32435 ; CHECK: bb.1 (%ir-block.0):436 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3437 ; CHECK-NEXT: {{ $}}438 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0439 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1440 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)441 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2442 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3443 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)444 ; CHECK-NEXT: [[SSHLSAT:%[0-9]+]]:_(<2 x s32>) = G_SSHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s32>)445 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SSHLSAT]](<2 x s32>)446 ; CHECK-NEXT: $vgpr0 = COPY [[UV]](s32)447 ; CHECK-NEXT: $vgpr1 = COPY [[UV1]](s32)448 ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1449 %res = call <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)450 ret <2 x i32> %res451}452declare <2 x i32> @llvm.sshl.sat.v2i32(<2 x i32>, <2 x i32>)453