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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel < %s | FileCheck %s3 4; early-tailduplication deletes cycle exit block created by structurize-cfg5; that had exactly one predecessor. Now, new cycle exit block has two6; predecessors, we need to find predecessor that belongs to the cycle.7 8define amdgpu_ps void @_amdgpu_ps_main(i1 %arg) {9; CHECK-LABEL: _amdgpu_ps_main:10; CHECK: ; %bb.0: ; %bb11; CHECK-NEXT: s_mov_b32 s4, 012; CHECK-NEXT: v_and_b32_e32 v0, 1, v013; CHECK-NEXT: s_mov_b32 s5, s414; CHECK-NEXT: s_mov_b32 s6, s415; CHECK-NEXT: s_mov_b32 s7, s416; CHECK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD017; CHECK-NEXT: s_buffer_load_dword s1, s[4:7], 0x018; CHECK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD119; CHECK-NEXT: s_mov_b32 s10, -120; CHECK-NEXT: s_mov_b32 s11, 0x31c1600021; CHECK-NEXT: s_add_u32 s8, s8, s022; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v023; CHECK-NEXT: s_addc_u32 s9, s9, 024; CHECK-NEXT: s_mov_b32 s32, 025; CHECK-NEXT: s_waitcnt lgkmcnt(0)26; CHECK-NEXT: s_cmp_ge_i32 s1, 027; CHECK-NEXT: s_cbranch_scc0 .LBB0_228; CHECK-NEXT: .LBB0_1: ; %bb1229; CHECK-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s430; CHECK-NEXT: v_mov_b32_e32 v1, 031; CHECK-NEXT: v_mov_b32_e32 v2, 032; CHECK-NEXT: v_mov_b32_e32 v3, 033; CHECK-NEXT: v_mov_b32_e32 v4, 034; CHECK-NEXT: s_mov_b64 s[0:1], s[8:9]35; CHECK-NEXT: s_mov_b64 s[2:3], s[10:11]36; CHECK-NEXT: s_swappc_b64 s[30:31], 037; CHECK-NEXT: .LBB0_2: ; %bb2.preheader38; CHECK-NEXT: s_mov_b32 s1, 039; CHECK-NEXT: v_mov_b32_e32 v0, s140; CHECK-NEXT: s_branch .LBB0_441; CHECK-NEXT: .p2align 642; CHECK-NEXT: .LBB0_3: ; %bb643; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=144; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s345; CHECK-NEXT: s_and_b32 s2, 1, s246; CHECK-NEXT: v_or_b32_e32 v1, 1, v047; CHECK-NEXT: v_cmp_ne_u32_e64 s2, 0, s248; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v049; CHECK-NEXT: v_mov_b32_e32 v0, v150; CHECK-NEXT: s_and_b32 s4, s2, s151; CHECK-NEXT: s_andn2_b32 s1, s1, exec_lo52; CHECK-NEXT: s_and_b32 s2, exec_lo, s453; CHECK-NEXT: s_or_b32 s1, s1, s254; CHECK-NEXT: s_cbranch_vccz .LBB0_155; CHECK-NEXT: .LBB0_4: ; %bb256; CHECK-NEXT: ; =>This Inner Loop Header: Depth=157; CHECK-NEXT: s_mov_b32 s2, 058; CHECK-NEXT: s_and_saveexec_b32 s3, s059; CHECK-NEXT: s_cbranch_execz .LBB0_360; CHECK-NEXT: ; %bb.5: ; %bb561; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=162; CHECK-NEXT: s_mov_b32 s2, 163; CHECK-NEXT: s_branch .LBB0_364bb:65 %i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0)66 %i1 = icmp slt i32 %i, 067 br i1 %i1, label %bb2, label %bb1268 69bb2:70 %i3 = phi i1 [ %i9, %bb6 ], [ false, %bb ]71 %i4 = phi i32 [ %i10, %bb6 ], [ 0, %bb ]72 br i1 %arg, label %bb5, label %bb673 74bb5:75 br label %bb676 77bb6:78 %i7 = phi i32 [ 0, %bb2 ], [ 1, %bb5 ]79 %i8 = icmp ne i32 %i7, 080 %i9 = select i1 %i8, i1 %i3, i1 false81 %i10 = or i32 %i4, 182 %i11 = icmp slt i32 %i4, 083 br i1 %i11, label %bb2, label %bb1284 85bb12:86 %i13 = phi i1 [ false, %bb ], [ %i9, %bb6 ]87 %i14 = select i1 %i13, float 0.000000e+00, float 1.000000e+0088 %i15 = insertelement <4 x float> zeroinitializer, float %i14, i64 089 call amdgpu_gfx addrspace(4) void null(<4 x float> %i15, i32 0)90 unreachable91}92 93declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg)94