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1; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-WGP %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s5; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s6; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s7; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,ALIGNED-CU %s8; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED %s9 10; GCN-LABEL: test_local_misaligned_v2:11; GCN-DAG: ds_{{read2|load_2addr}}_b3212; GCN-DAG: ds_{{write2|store_2addr}}_b3213define amdgpu_kernel void @test_local_misaligned_v2(ptr addrspace(3) %arg) {14bb:15 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()16 %gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid17 %load = load <2 x i32>, ptr addrspace(3) %gep, align 418 %v1 = extractelement <2 x i32> %load, i32 019 %v2 = extractelement <2 x i32> %load, i32 120 %v3 = insertelement <2 x i32> poison, i32 %v2, i32 021 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 122 store <2 x i32> %v4, ptr addrspace(3) %gep, align 423 ret void24}25 26; GCN-LABEL: test_local_misaligned_v4:27; ALIGNED-DAG: ds_{{read2|load_2addr}}_b3228; ALIGNED-DAG: ds_{{read2|load_2addr}}_b3229; ALIGNED-DAG: ds_{{write2|store_2addr}}_b3230; ALIGNED-DAG: ds_{{write2|store_2addr}}_b3231; UNALIGNED-DAG: ds_{{read2|load_2addr}}_b6432; UNALIGNED-DAG: ds_{{write2|store_2addr}}_b6433define amdgpu_kernel void @test_local_misaligned_v4(ptr addrspace(3) %arg) {34bb:35 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()36 %gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid37 %load = load <4 x i32>, ptr addrspace(3) %gep, align 438 %v1 = extractelement <4 x i32> %load, i32 039 %v2 = extractelement <4 x i32> %load, i32 140 %v3 = extractelement <4 x i32> %load, i32 241 %v4 = extractelement <4 x i32> %load, i32 342 %v5 = insertelement <4 x i32> poison, i32 %v4, i32 043 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 144 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 245 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 346 store <4 x i32> %v8, ptr addrspace(3) %gep, align 447 ret void48}49 50; GCN-LABEL: test_local_misaligned_v3:51; ALIGNED-DAG: ds_{{read2|load_2addr}}_b3252; ALIGNED-DAG: ds_{{read|load}}_b3253; ALIGNED-DAG: ds_{{write2|store_2addr}}_b3254; ALIGNED-DAG: ds_{{write|store}}_b3255; UNALIGNED-DAG: ds_{{read|load}}_b9656; UNALIGNED-DAG: ds_{{write|store}}_b9657define amdgpu_kernel void @test_local_misaligned_v3(ptr addrspace(3) %arg) {58bb:59 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()60 %gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid61 %load = load <3 x i32>, ptr addrspace(3) %gep, align 462 %v1 = extractelement <3 x i32> %load, i32 063 %v2 = extractelement <3 x i32> %load, i32 164 %v3 = extractelement <3 x i32> %load, i32 265 %v5 = insertelement <3 x i32> poison, i32 %v3, i32 066 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 167 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 268 store <3 x i32> %v7, ptr addrspace(3) %gep, align 469 ret void70}71 72; GCN-LABEL: test_local_aligned_v2:73; GCN-DAG: ds_{{read|load}}_b6474; GCN-DAG: ds_{{write|store}}_b6475define amdgpu_kernel void @test_local_aligned_v2(ptr addrspace(3) %arg) {76bb:77 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()78 %gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid79 %load = load <2 x i32>, ptr addrspace(3) %gep, align 880 %v1 = extractelement <2 x i32> %load, i32 081 %v2 = extractelement <2 x i32> %load, i32 182 %v3 = insertelement <2 x i32> poison, i32 %v2, i32 083 %v4 = insertelement <2 x i32> %v3, i32 %v1, i32 184 store <2 x i32> %v4, ptr addrspace(3) %gep, align 885 ret void86}87 88; GCN-LABEL: test_local_aligned_v3:89; GCN-DAG: ds_{{read|load}}_b9690; GCN-DAG: ds_{{write|store}}_b9691define amdgpu_kernel void @test_local_aligned_v3(ptr addrspace(3) %arg) {92bb:93 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()94 %gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid95 %load = load <3 x i32>, ptr addrspace(3) %gep, align 1696 %v1 = extractelement <3 x i32> %load, i32 097 %v2 = extractelement <3 x i32> %load, i32 198 %v3 = extractelement <3 x i32> %load, i32 299 %v5 = insertelement <3 x i32> poison, i32 %v3, i32 0100 %v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1101 %v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2102 store <3 x i32> %v7, ptr addrspace(3) %gep, align 16103 ret void104}105 106; GCN-LABEL: test_local_v4_aligned8:107; ALIGNED-WGP-DAG: ds_{{read2|load_2addr}}_b32108; ALIGNED-WGP-DAG: ds_{{read2|load_2addr}}_b32109; ALIGNED-WGP-DAG: ds_{{write2|store_2addr}}_b32110; ALIGNED-WGP-DAG: ds_{{write2|store_2addr}}_b32111; ALIGNED-CU-DAG: ds_{{read2|load_2addr}}_b64112; ALIGNED-CU-DAG: ds_{{write2|store_2addr}}_b64113; UNALIGNED-DAG: ds_{{read2|load_2addr}}_b64114; UNALIGNED-DAG: ds_{{write2|store_2addr}}_b64115define amdgpu_kernel void @test_local_v4_aligned8(ptr addrspace(3) %arg) {116bb:117 %lid = tail call i32 @llvm.amdgcn.workitem.id.x()118 %gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid119 %load = load <4 x i32>, ptr addrspace(3) %gep, align 8120 %v1 = extractelement <4 x i32> %load, i32 0121 %v2 = extractelement <4 x i32> %load, i32 1122 %v3 = extractelement <4 x i32> %load, i32 2123 %v4 = extractelement <4 x i32> %load, i32 3124 %v5 = insertelement <4 x i32> poison, i32 %v4, i32 0125 %v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1126 %v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2127 %v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3128 store <4 x i32> %v8, ptr addrspace(3) %gep, align 8129 ret void130}131 132declare i32 @llvm.amdgcn.workitem.id.x()133