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1# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=2 -pass-remarks-missed='gisel*' -filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s2 3# Make sure incorrect usage of control flow intrinsics fails to select in case some transform separated the intrinsic from its branch.4 5# ERR: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_different_block)6# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_not_brcond_user)7# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: si_if_multi_user)8# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_xor_0)9# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_or_neg1)10# ERR-NEXT: remark: <unknown>:0:0: unable to legalize instruction: %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2:_(s1) (in function: brcond_si_if_negated_multi_use)11 12 13---14name: brcond_si_if_different_block15body: |16 bb.0:17 successors: %bb.118 liveins: $vgpr0, $vgpr119 %0:_(s32) = COPY $vgpr020 %1:_(s32) = COPY $vgpr121 %2:_(s1) = G_ICMP intpred(ne), %0, %122 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %223 24 bb.1:25 G_BRCOND %3, %bb.126 27...28 29---30name: si_if_not_brcond_user31body: |32 bb.0:33 liveins: $vgpr0, $vgpr134 %0:_(s32) = COPY $vgpr035 %1:_(s32) = COPY $vgpr136 %2:_(s1) = G_ICMP intpred(ne), %0, %137 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %238 %5:_(s32) = G_SELECT %3, %0, %139 S_ENDPGM 0, implicit %540 41...42 43---44name: si_if_multi_user45body: |46 bb.0:47 liveins: $vgpr0, $vgpr148 %0:_(s32) = COPY $vgpr049 %1:_(s32) = COPY $vgpr150 %2:_(s1) = G_ICMP intpred(ne), %0, %151 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %252 %5:_(s32) = G_SELECT %3, %0, %153 G_BRCOND %3, %bb.154 55 bb.1:56 S_ENDPGM 0, implicit %557 58...59 60# Make sure we only match G_XOR (if), -161---62name: brcond_si_if_xor_063body: |64 bb.0:65 successors: %bb.166 liveins: $vgpr0, $vgpr167 %0:_(s32) = COPY $vgpr068 %1:_(s32) = COPY $vgpr169 %2:_(s1) = G_ICMP intpred(ne), %0, %170 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %271 %5:_(s1) = G_CONSTANT i1 false72 %6:_(s1) = G_XOR %3, %573 G_BRCOND %6, %bb.274 G_BR %bb.375 76 bb.1:77 S_NOP 078 79 bb.2:80 S_NOP 181 82 bb.3:83 S_NOP 284...85 86# Make sure we only match G_XOR (if), -187---88name: brcond_si_if_or_neg189body: |90 bb.0:91 successors: %bb.192 liveins: $vgpr0, $vgpr193 %0:_(s32) = COPY $vgpr094 %1:_(s32) = COPY $vgpr195 %2:_(s1) = G_ICMP intpred(ne), %0, %196 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %297 %5:_(s1) = G_CONSTANT i1 true98 %6:_(s1) = G_OR %3, %599 G_BRCOND %6, %bb.2100 G_BR %bb.3101 102 bb.1:103 S_NOP 0104 105 bb.2:106 S_NOP 1107 108 bb.3:109 S_NOP 2110...111 112---113name: brcond_si_if_negated_multi_use114body: |115 bb.0:116 successors: %bb.1117 liveins: $vgpr0, $vgpr1118 %0:_(s32) = COPY $vgpr0119 %1:_(s32) = COPY $vgpr1120 %2:_(s1) = G_ICMP intpred(ne), %0, %1121 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2122 %5:_(s1) = G_CONSTANT i1 true123 %6:_(s1) = G_XOR %3, %5124 S_NOP 0, implicit %6125 G_BRCOND %6, %bb.2126 G_BR %bb.3127 128 bb.1:129 S_NOP 0130 131 bb.2:132 S_NOP 1133 134 bb.3:135 S_NOP 2136...137