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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s4 5---6name: test_rsq_clamp_flags_ieee_on_f327tracksRegLiveness: true8machineFunctionInfo:9 mode:10 ieee: true11 12body: |13 bb.0:14 liveins: $vgpr015 16 ; SI-LABEL: name: test_rsq_clamp_flags_ieee_on_f3217 ; SI: liveins: $vgpr018 ; SI-NEXT: {{ $}}19 ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr020 ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32)21 ; SI-NEXT: $vgpr0 = COPY [[INT]](s32)22 ; VI-LABEL: name: test_rsq_clamp_flags_ieee_on_f3223 ; VI: liveins: $vgpr024 ; VI-NEXT: {{ $}}25 ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr026 ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)27 ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE000000028 ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]]29 ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE000000030 ; VI-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]31 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)32 %0:_(s32) = COPY $vgpr033 %1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %034 $vgpr0 = COPY %135...36 37---38name: test_rsq_clamp_flags_ieee_off_f3239tracksRegLiveness: true40machineFunctionInfo:41 mode:42 ieee: false43 44body: |45 bb.0:46 liveins: $vgpr047 48 ; SI-LABEL: name: test_rsq_clamp_flags_ieee_off_f3249 ; SI: liveins: $vgpr050 ; SI-NEXT: {{ $}}51 ; SI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr052 ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32)53 ; SI-NEXT: $vgpr0 = COPY [[INT]](s32)54 ; VI-LABEL: name: test_rsq_clamp_flags_ieee_off_f3255 ; VI: liveins: $vgpr056 ; VI-NEXT: {{ $}}57 ; VI-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr058 ; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)59 ; VI-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE000000060 ; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]61 ; VI-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE000000062 ; VI-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]63 ; VI-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)64 %0:_(s32) = COPY $vgpr065 %1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %066 $vgpr0 = COPY %167...68