172 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx90a -run-pass=legalizer -o - %s | FileCheck -check-prefix=GCN %s3 4--- |5 define amdgpu_kernel void @test_workitem_id_x_unpacked() !reqd_work_group_size !0 {6 ret void7 }8 9 define amdgpu_kernel void @test_workitem_id_y_unpacked() !reqd_work_group_size !0 {10 ret void11 }12 13 define amdgpu_kernel void @test_workitem_id_z_unpacked() !reqd_work_group_size !0 {14 ret void15 }16 17 define amdgpu_kernel void @test_workitem_id_x_packed() !reqd_work_group_size !0 {18 ret void19 }20 21 define amdgpu_kernel void @test_workitem_id_y_packed() !reqd_work_group_size !0 {22 ret void23 }24 25 define amdgpu_kernel void @test_workitem_id_z_packed() !reqd_work_group_size !0 {26 ret void27 }28 29 define amdgpu_kernel void @missing_arg_info() "amdgpu-no-workitem-id-x" {30 ret void31 }32 33 !0 = !{i32 256, i32 8, i32 4}34...35---36name: test_workitem_id_x_unpacked37machineFunctionInfo:38 argumentInfo:39 workGroupIDX: { reg: '$sgpr2' }40 workItemIDX: { reg: '$vgpr0' }41 workItemIDY: { reg: '$vgpr1' }42 workItemIDZ: { reg: '$vgpr2' }43body: |44 bb.0:45 ; GCN-LABEL: name: test_workitem_id_x_unpacked46 ; GCN: liveins: $vgpr047 ; GCN-NEXT: {{ $}}48 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr049 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)50 ; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 851 ; GCN-NEXT: S_ENDPGM 0, implicit [[ASSERT_ZEXT]](s32)52 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)53 S_ENDPGM 0, implicit %054...55 56---57name: test_workitem_id_y_unpacked58machineFunctionInfo:59 argumentInfo:60 workGroupIDX: { reg: '$sgpr2' }61 workItemIDX: { reg: '$vgpr0' }62 workItemIDY: { reg: '$vgpr1' }63 workItemIDZ: { reg: '$vgpr2' }64body: |65 bb.0:66 ; GCN-LABEL: name: test_workitem_id_y_unpacked67 ; GCN: liveins: $vgpr168 ; GCN-NEXT: {{ $}}69 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr170 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)71 ; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 372 ; GCN-NEXT: S_ENDPGM 0, implicit [[ASSERT_ZEXT]](s32)73 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.y)74 S_ENDPGM 0, implicit %075...76 77---78name: test_workitem_id_z_unpacked79machineFunctionInfo:80 argumentInfo:81 workGroupIDX: { reg: '$sgpr2' }82 workItemIDX: { reg: '$vgpr0' }83 workItemIDY: { reg: '$vgpr1' }84 workItemIDZ: { reg: '$vgpr2' }85body: |86 bb.0:87 ; GCN-LABEL: name: test_workitem_id_z_unpacked88 ; GCN: liveins: $vgpr289 ; GCN-NEXT: {{ $}}90 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr291 ; GCN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)92 ; GCN-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 293 ; GCN-NEXT: S_ENDPGM 0, implicit [[ASSERT_ZEXT]](s32)94 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.z)95 S_ENDPGM 0, implicit %096...97 98---99name: test_workitem_id_x_packed100machineFunctionInfo:101 argumentInfo:102 workItemIDX: { reg: '$vgpr0', mask: 1023 }103 workItemIDY: { reg: '$vgpr0', mask: 1047552 }104 workItemIDZ: { reg: '$vgpr0', mask: 1072693248 }105body: |106 bb.0:107 ; GCN-LABEL: name: test_workitem_id_x_packed108 ; GCN: liveins: $vgpr0109 ; GCN-NEXT: {{ $}}110 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0111 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023112 ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]113 ; GCN-NEXT: S_ENDPGM 0, implicit [[AND]](s32)114 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)115 S_ENDPGM 0, implicit %0116...117 118---119name: test_workitem_id_y_packed120machineFunctionInfo:121 argumentInfo:122 workItemIDX: { reg: '$vgpr0', mask: 1023 }123 workItemIDY: { reg: '$vgpr0', mask: 1047552 }124 workItemIDZ: { reg: '$vgpr0', mask: 1072693248 }125body: |126 bb.0:127 ; GCN-LABEL: name: test_workitem_id_y_packed128 ; GCN: liveins: $vgpr0129 ; GCN-NEXT: {{ $}}130 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0131 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10132 ; GCN-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)133 ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023134 ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]135 ; GCN-NEXT: S_ENDPGM 0, implicit [[AND]](s32)136 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.y)137 S_ENDPGM 0, implicit %0138...139 140---141name: test_workitem_id_z_packed142machineFunctionInfo:143 argumentInfo:144 workItemIDX: { reg: '$vgpr0', mask: 1023 }145 workItemIDY: { reg: '$vgpr0', mask: 1047552 }146 workItemIDZ: { reg: '$vgpr0', mask: 1072693248 }147body: |148 bb.0:149 ; GCN-LABEL: name: test_workitem_id_z_packed150 ; GCN: liveins: $vgpr0151 ; GCN-NEXT: {{ $}}152 ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0153 ; GCN-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20154 ; GCN-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)155 ; GCN-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023156 ; GCN-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]157 ; GCN-NEXT: S_ENDPGM 0, implicit [[AND]](s32)158 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.z)159 S_ENDPGM 0, implicit %0160...161 162---163name: missing_arg_info164body: |165 bb.0:166 ; GCN-LABEL: name: missing_arg_info167 ; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF168 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]](s32)169 %0:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.z)170 S_ENDPGM 0, implicit %0171...172