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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -o - %s | FileCheck %s3# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -filetype=null %s 2>&1 | FileCheck -check-prefix=ERROR %s4 5# ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_XCHG %0:_(p0), %1:_ :: (load store seq_cst (s32)) (in function: atomicrmw_xchg_flat_i32)6 7 8---9name: atomicrmw_xchg_flat_i3210 11body: |12 bb.0:13 liveins: $sgpr0_sgpr1, $sgpr214 ; CHECK-LABEL: name: atomicrmw_xchg_flat_i3215 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr216 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr219 ; CHECK-NEXT: [[ATOMICRMW_XCHG:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))20 %0:_(p0) = COPY $sgpr0_sgpr121 %1:_(s32) = COPY $sgpr222 %2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst (s32), addrspace 0)23...24 25---26name: atomicrmw_xchg_flat_i6427 28body: |29 bb.0:30 liveins: $sgpr0_sgpr1, $sgpr231 ; CHECK-LABEL: name: atomicrmw_xchg_flat_i6432 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr233 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr236 ; CHECK-NEXT: [[ATOMICRMW_XCHG:%[0-9]+]]:_(s32) = G_ATOMICRMW_XCHG [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))37 %0:_(p0) = COPY $sgpr0_sgpr138 %1:_(s32) = COPY $sgpr239 %2:_(s32) = G_ATOMICRMW_XCHG %0, %1 :: (load store seq_cst (s32), addrspace 0)40...41