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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s4# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -O0 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s5 6---7name: legal_brcond_vcc8body: |9 ; WAVE64-LABEL: name: legal_brcond_vcc10 ; WAVE64: bb.0:11 ; WAVE64-NEXT: successors: %bb.1(0x80000000)12 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr113 ; WAVE64-NEXT: {{ $}}14 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr015 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr116 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]17 ; WAVE64-NEXT: G_BRCOND [[ICMP]](s1), %bb.118 ; WAVE64-NEXT: {{ $}}19 ; WAVE64-NEXT: bb.1:20 ; WAVE32-LABEL: name: legal_brcond_vcc21 ; WAVE32: bb.0:22 ; WAVE32-NEXT: successors: %bb.1(0x80000000)23 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr124 ; WAVE32-NEXT: {{ $}}25 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr026 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr127 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]28 ; WAVE32-NEXT: G_BRCOND [[ICMP]](s1), %bb.129 ; WAVE32-NEXT: {{ $}}30 ; WAVE32-NEXT: bb.1:31 bb.0:32 successors: %bb.133 liveins: $vgpr0, $vgpr134 %0:_(s32) = COPY $vgpr035 %1:_(s32) = COPY $vgpr136 %2:_(s1) = G_ICMP intpred(ne), %0, %137 G_BRCOND %2, %bb.138 39 bb.1:40...41 42---43 44name: legal_brcond_sgpr_s145 46body: |47 ; WAVE64-LABEL: name: legal_brcond_sgpr_s148 ; WAVE64: bb.0:49 ; WAVE64-NEXT: successors: %bb.1(0x80000000)50 ; WAVE64-NEXT: liveins: $sgpr0, $sgpr151 ; WAVE64-NEXT: {{ $}}52 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr053 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr154 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]55 ; WAVE64-NEXT: G_BRCOND [[ICMP]](s1), %bb.156 ; WAVE64-NEXT: {{ $}}57 ; WAVE64-NEXT: bb.1:58 ; WAVE32-LABEL: name: legal_brcond_sgpr_s159 ; WAVE32: bb.0:60 ; WAVE32-NEXT: successors: %bb.1(0x80000000)61 ; WAVE32-NEXT: liveins: $sgpr0, $sgpr162 ; WAVE32-NEXT: {{ $}}63 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr064 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr165 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]66 ; WAVE32-NEXT: G_BRCOND [[ICMP]](s1), %bb.167 ; WAVE32-NEXT: {{ $}}68 ; WAVE32-NEXT: bb.1:69 bb.0:70 liveins: $sgpr0, $sgpr171 72 %0:_(s32) = COPY $sgpr073 %1:_(s32) = COPY $sgpr174 %2:_(s1) = G_ICMP intpred(eq), %0, %175 G_BRCOND %2, %bb.176 77 bb.1:78 79...80 81---82 83name: legal_brcond_sgpr_s3284 85body: |86 ; WAVE64-LABEL: name: legal_brcond_sgpr_s3287 ; WAVE64: bb.0:88 ; WAVE64-NEXT: successors: %bb.1(0x80000000)89 ; WAVE64-NEXT: liveins: $sgpr0, $sgpr190 ; WAVE64-NEXT: {{ $}}91 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr092 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr193 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]94 ; WAVE64-NEXT: G_BRCOND [[ICMP]](s32), %bb.195 ; WAVE64-NEXT: {{ $}}96 ; WAVE64-NEXT: bb.1:97 ; WAVE32-LABEL: name: legal_brcond_sgpr_s3298 ; WAVE32: bb.0:99 ; WAVE32-NEXT: successors: %bb.1(0x80000000)100 ; WAVE32-NEXT: liveins: $sgpr0, $sgpr1101 ; WAVE32-NEXT: {{ $}}102 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0103 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1104 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]105 ; WAVE32-NEXT: G_BRCOND [[ICMP]](s32), %bb.1106 ; WAVE32-NEXT: {{ $}}107 ; WAVE32-NEXT: bb.1:108 bb.0:109 liveins: $sgpr0, $sgpr1110 111 %0:_(s32) = COPY $sgpr0112 %1:_(s32) = COPY $sgpr1113 %2:_(s32) = G_ICMP intpred(eq), %0, %1114 G_BRCOND %2, %bb.1115 116 bb.1:117 118...119 120---121name: brcond_si_if122body: |123 ; WAVE64-LABEL: name: brcond_si_if124 ; WAVE64: bb.0:125 ; WAVE64-NEXT: successors: %bb.1(0x80000000)126 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1127 ; WAVE64-NEXT: {{ $}}128 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0129 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1130 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]131 ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec132 ; WAVE64-NEXT: G_BR %bb.1133 ; WAVE64-NEXT: {{ $}}134 ; WAVE64-NEXT: bb.1:135 ; WAVE32-LABEL: name: brcond_si_if136 ; WAVE32: bb.0:137 ; WAVE32-NEXT: successors: %bb.1(0x80000000)138 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1139 ; WAVE32-NEXT: {{ $}}140 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0141 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1142 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]143 ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec144 ; WAVE32-NEXT: G_BR %bb.1145 ; WAVE32-NEXT: {{ $}}146 ; WAVE32-NEXT: bb.1:147 bb.0:148 successors: %bb.1149 liveins: $vgpr0, $vgpr1150 %0:_(s32) = COPY $vgpr0151 %1:_(s32) = COPY $vgpr1152 %2:_(s1) = G_ICMP intpred(ne), %0, %1153 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2154 G_BRCOND %3, %bb.1155 156 bb.1:157...158 159---160name: brcond_si_else161body: |162 ; WAVE64-LABEL: name: brcond_si_else163 ; WAVE64: bb.0:164 ; WAVE64-NEXT: successors: %bb.1(0x80000000)165 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1166 ; WAVE64-NEXT: {{ $}}167 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0168 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1169 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]170 ; WAVE64-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_64_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec171 ; WAVE64-NEXT: G_BR %bb.1172 ; WAVE64-NEXT: {{ $}}173 ; WAVE64-NEXT: bb.1:174 ; WAVE32-LABEL: name: brcond_si_else175 ; WAVE32: bb.0:176 ; WAVE32-NEXT: successors: %bb.1(0x80000000)177 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1178 ; WAVE32-NEXT: {{ $}}179 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0180 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1181 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]182 ; WAVE32-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_ELSE [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec183 ; WAVE32-NEXT: G_BR %bb.1184 ; WAVE32-NEXT: {{ $}}185 ; WAVE32-NEXT: bb.1:186 bb.0:187 successors: %bb.1188 liveins: $vgpr0, $vgpr1189 %0:_(s32) = COPY $vgpr0190 %1:_(s32) = COPY $vgpr1191 %2:_(s1) = G_ICMP intpred(ne), %0, %1192 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.else), %2193 G_BRCOND %3, %bb.1194 195 bb.1:196...197 198---199name: brcond_si_loop_brcond200tracksRegLiveness: true201body: |202 ; WAVE64-LABEL: name: brcond_si_loop_brcond203 ; WAVE64: bb.0:204 ; WAVE64-NEXT: successors: %bb.1(0x80000000)205 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1206 ; WAVE64-NEXT: {{ $}}207 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0208 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1209 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1210 ; WAVE64-NEXT: {{ $}}211 ; WAVE64-NEXT: bb.1:212 ; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)213 ; WAVE64-NEXT: {{ $}}214 ; WAVE64-NEXT: S_NOP 0215 ; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec216 ; WAVE64-NEXT: G_BR %bb.2217 ; WAVE64-NEXT: {{ $}}218 ; WAVE64-NEXT: bb.2:219 ; WAVE64-NEXT: S_NOP 0220 ; WAVE32-LABEL: name: brcond_si_loop_brcond221 ; WAVE32: bb.0:222 ; WAVE32-NEXT: successors: %bb.1(0x80000000)223 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1224 ; WAVE32-NEXT: {{ $}}225 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0226 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1227 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1228 ; WAVE32-NEXT: {{ $}}229 ; WAVE32-NEXT: bb.1:230 ; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)231 ; WAVE32-NEXT: {{ $}}232 ; WAVE32-NEXT: S_NOP 0233 ; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec234 ; WAVE32-NEXT: G_BR %bb.2235 ; WAVE32-NEXT: {{ $}}236 ; WAVE32-NEXT: bb.2:237 ; WAVE32-NEXT: S_NOP 0238 bb.0:239 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1240 %0:_(s32) = COPY $vgpr0241 %1:_(s32) = COPY $vgpr1242 %2:_(s64) = COPY $sgpr0_sgpr1243 244 bb.1:245 successors: %bb.1, %bb.2246 S_NOP 0247 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2248 G_BRCOND %3, %bb.2249 G_BR %bb.1250 251 bb.2:252 S_NOP 0253...254 255# This usage is backwards from how the intrinsic is supposed to be256# used.257---258name: brcond_si_loop_brcond_back259tracksRegLiveness: true260body: |261 ; WAVE64-LABEL: name: brcond_si_loop_brcond_back262 ; WAVE64: bb.0:263 ; WAVE64-NEXT: successors: %bb.1(0x80000000)264 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1265 ; WAVE64-NEXT: {{ $}}266 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0267 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1268 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1269 ; WAVE64-NEXT: {{ $}}270 ; WAVE64-NEXT: bb.1:271 ; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)272 ; WAVE64-NEXT: {{ $}}273 ; WAVE64-NEXT: S_NOP 0274 ; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec275 ; WAVE64-NEXT: G_BR %bb.1276 ; WAVE64-NEXT: {{ $}}277 ; WAVE64-NEXT: bb.2:278 ; WAVE64-NEXT: S_NOP 0279 ; WAVE32-LABEL: name: brcond_si_loop_brcond_back280 ; WAVE32: bb.0:281 ; WAVE32-NEXT: successors: %bb.1(0x80000000)282 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1283 ; WAVE32-NEXT: {{ $}}284 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0285 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1286 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1287 ; WAVE32-NEXT: {{ $}}288 ; WAVE32-NEXT: bb.1:289 ; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)290 ; WAVE32-NEXT: {{ $}}291 ; WAVE32-NEXT: S_NOP 0292 ; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec293 ; WAVE32-NEXT: G_BR %bb.1294 ; WAVE32-NEXT: {{ $}}295 ; WAVE32-NEXT: bb.2:296 ; WAVE32-NEXT: S_NOP 0297 bb.0:298 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1299 %0:_(s32) = COPY $vgpr0300 %1:_(s32) = COPY $vgpr1301 %2:_(s64) = COPY $sgpr0_sgpr1302 303 bb.1:304 successors: %bb.1, %bb.2305 S_NOP 0306 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2307 G_BRCOND %3, %bb.1308 G_BR %bb.2309 310 bb.2:311 S_NOP 0312...313 314# This usage is backwards from how the intrinsic is supposed to be315# used.316---317name: brcond_si_loop_brcond_back_fallthrough318tracksRegLiveness: true319body: |320 ; WAVE64-LABEL: name: brcond_si_loop_brcond_back_fallthrough321 ; WAVE64: bb.0:322 ; WAVE64-NEXT: successors: %bb.1(0x80000000)323 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1324 ; WAVE64-NEXT: {{ $}}325 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0326 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1327 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1328 ; WAVE64-NEXT: {{ $}}329 ; WAVE64-NEXT: bb.1:330 ; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)331 ; WAVE64-NEXT: {{ $}}332 ; WAVE64-NEXT: S_NOP 0333 ; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec334 ; WAVE64-NEXT: G_BR %bb.1335 ; WAVE64-NEXT: {{ $}}336 ; WAVE64-NEXT: bb.2:337 ; WAVE32-LABEL: name: brcond_si_loop_brcond_back_fallthrough338 ; WAVE32: bb.0:339 ; WAVE32-NEXT: successors: %bb.1(0x80000000)340 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1341 ; WAVE32-NEXT: {{ $}}342 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0343 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1344 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1345 ; WAVE32-NEXT: {{ $}}346 ; WAVE32-NEXT: bb.1:347 ; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)348 ; WAVE32-NEXT: {{ $}}349 ; WAVE32-NEXT: S_NOP 0350 ; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec351 ; WAVE32-NEXT: G_BR %bb.1352 ; WAVE32-NEXT: {{ $}}353 ; WAVE32-NEXT: bb.2:354 bb.0:355 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1356 %0:_(s32) = COPY $vgpr0357 %1:_(s32) = COPY $vgpr1358 %2:_(s64) = COPY $sgpr0_sgpr1359 360 bb.1:361 successors: %bb.1, %bb.2362 S_NOP 0363 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2364 G_BRCOND %3, %bb.1365 366 bb.2:367...368 369# There's another instruction between the intrinsic and the370# conditional branch, so we need to move the insert point.371---372name: brcond_si_if_need_insert_terminator_point373body: |374 ; WAVE64-LABEL: name: brcond_si_if_need_insert_terminator_point375 ; WAVE64: bb.0:376 ; WAVE64-NEXT: successors: %bb.1(0x80000000)377 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2378 ; WAVE64-NEXT: {{ $}}379 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0380 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1381 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]382 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2383 ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec384 ; WAVE64-NEXT: G_BR %bb.1385 ; WAVE64-NEXT: {{ $}}386 ; WAVE64-NEXT: bb.1:387 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY2]](s32)388 ; WAVE32-LABEL: name: brcond_si_if_need_insert_terminator_point389 ; WAVE32: bb.0:390 ; WAVE32-NEXT: successors: %bb.1(0x80000000)391 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2392 ; WAVE32-NEXT: {{ $}}393 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0394 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1395 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]396 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2397 ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec398 ; WAVE32-NEXT: G_BR %bb.1399 ; WAVE32-NEXT: {{ $}}400 ; WAVE32-NEXT: bb.1:401 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY2]](s32)402 bb.0:403 successors: %bb.1404 liveins: $vgpr0, $vgpr1, $vgpr2405 %0:_(s32) = COPY $vgpr0406 %1:_(s32) = COPY $vgpr1407 %2:_(s1) = G_ICMP intpred(ne), %0, %1408 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2409 %5:_(s32) = COPY $vgpr2410 G_BRCOND %3, %bb.1411 412 bb.1:413 S_ENDPGM 0, implicit %5414...415 416---417name: brcond_si_loop_need_terminator_insert_point418tracksRegLiveness: true419body: |420 ; WAVE64-LABEL: name: brcond_si_loop_need_terminator_insert_point421 ; WAVE64: bb.0:422 ; WAVE64-NEXT: successors: %bb.1(0x80000000)423 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1424 ; WAVE64-NEXT: {{ $}}425 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0426 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1427 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1428 ; WAVE64-NEXT: {{ $}}429 ; WAVE64-NEXT: bb.1:430 ; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)431 ; WAVE64-NEXT: {{ $}}432 ; WAVE64-NEXT: S_NOP 0433 ; WAVE64-NEXT: S_NOP 0434 ; WAVE64-NEXT: S_NOP 0435 ; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec436 ; WAVE64-NEXT: G_BR %bb.2437 ; WAVE64-NEXT: {{ $}}438 ; WAVE64-NEXT: bb.2:439 ; WAVE64-NEXT: S_NOP 0440 ; WAVE32-LABEL: name: brcond_si_loop_need_terminator_insert_point441 ; WAVE32: bb.0:442 ; WAVE32-NEXT: successors: %bb.1(0x80000000)443 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1444 ; WAVE32-NEXT: {{ $}}445 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0446 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1447 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1448 ; WAVE32-NEXT: {{ $}}449 ; WAVE32-NEXT: bb.1:450 ; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)451 ; WAVE32-NEXT: {{ $}}452 ; WAVE32-NEXT: S_NOP 0453 ; WAVE32-NEXT: S_NOP 0454 ; WAVE32-NEXT: S_NOP 0455 ; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec456 ; WAVE32-NEXT: G_BR %bb.2457 ; WAVE32-NEXT: {{ $}}458 ; WAVE32-NEXT: bb.2:459 ; WAVE32-NEXT: S_NOP 0460 bb.0:461 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1462 %0:_(s32) = COPY $vgpr0463 %1:_(s32) = COPY $vgpr1464 %2:_(s64) = COPY $sgpr0_sgpr1465 466 bb.1:467 successors: %bb.1, %bb.2468 S_NOP 0469 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2470 S_NOP 0471 S_NOP 0472 G_BRCOND %3, %bb.2473 G_BR %bb.1474 475 bb.2:476 S_NOP 0477...478 479---480name: brcond_si_if_negated481body: |482 ; WAVE64-LABEL: name: brcond_si_if_negated483 ; WAVE64: bb.0:484 ; WAVE64-NEXT: successors: %bb.1(0x80000000)485 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1486 ; WAVE64-NEXT: {{ $}}487 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0488 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1489 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]490 ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec491 ; WAVE64-NEXT: G_BR %bb.1492 ; WAVE64-NEXT: {{ $}}493 ; WAVE64-NEXT: bb.1:494 ; WAVE64-NEXT: successors: %bb.2(0x80000000)495 ; WAVE64-NEXT: {{ $}}496 ; WAVE64-NEXT: S_NOP 0497 ; WAVE64-NEXT: {{ $}}498 ; WAVE64-NEXT: bb.2:499 ; WAVE64-NEXT: S_NOP 1500 ; WAVE32-LABEL: name: brcond_si_if_negated501 ; WAVE32: bb.0:502 ; WAVE32-NEXT: successors: %bb.1(0x80000000)503 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1504 ; WAVE32-NEXT: {{ $}}505 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0506 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1507 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]508 ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec509 ; WAVE32-NEXT: G_BR %bb.1510 ; WAVE32-NEXT: {{ $}}511 ; WAVE32-NEXT: bb.1:512 ; WAVE32-NEXT: successors: %bb.2(0x80000000)513 ; WAVE32-NEXT: {{ $}}514 ; WAVE32-NEXT: S_NOP 0515 ; WAVE32-NEXT: {{ $}}516 ; WAVE32-NEXT: bb.2:517 ; WAVE32-NEXT: S_NOP 1518 bb.0:519 successors: %bb.1520 liveins: $vgpr0, $vgpr1521 %0:_(s32) = COPY $vgpr0522 %1:_(s32) = COPY $vgpr1523 %2:_(s1) = G_ICMP intpred(ne), %0, %1524 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2525 %5:_(s1) = G_CONSTANT i1 true526 %6:_(s1) = G_XOR %3, %5527 G_BRCOND %6, %bb.2528 529 bb.1:530 S_NOP 0531 532 bb.2:533 S_NOP 1534...535 536---537name: brcond_si_if_br_negated538body: |539 ; WAVE64-LABEL: name: brcond_si_if_br_negated540 ; WAVE64: bb.0:541 ; WAVE64-NEXT: successors: %bb.1(0x80000000)542 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1543 ; WAVE64-NEXT: {{ $}}544 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0545 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1546 ; WAVE64-NEXT: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]547 ; WAVE64-NEXT: [[SI_IF:%[0-9]+]]:sreg_64_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec548 ; WAVE64-NEXT: G_BR %bb.3549 ; WAVE64-NEXT: {{ $}}550 ; WAVE64-NEXT: bb.1:551 ; WAVE64-NEXT: successors: %bb.2(0x80000000)552 ; WAVE64-NEXT: {{ $}}553 ; WAVE64-NEXT: S_NOP 0554 ; WAVE64-NEXT: {{ $}}555 ; WAVE64-NEXT: bb.2:556 ; WAVE64-NEXT: successors: %bb.3(0x80000000)557 ; WAVE64-NEXT: {{ $}}558 ; WAVE64-NEXT: S_NOP 1559 ; WAVE64-NEXT: {{ $}}560 ; WAVE64-NEXT: bb.3:561 ; WAVE64-NEXT: S_NOP 2562 ; WAVE32-LABEL: name: brcond_si_if_br_negated563 ; WAVE32: bb.0:564 ; WAVE32-NEXT: successors: %bb.1(0x80000000)565 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1566 ; WAVE32-NEXT: {{ $}}567 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0568 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1569 ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]570 ; WAVE32-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s64) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec571 ; WAVE32-NEXT: G_BR %bb.3572 ; WAVE32-NEXT: {{ $}}573 ; WAVE32-NEXT: bb.1:574 ; WAVE32-NEXT: successors: %bb.2(0x80000000)575 ; WAVE32-NEXT: {{ $}}576 ; WAVE32-NEXT: S_NOP 0577 ; WAVE32-NEXT: {{ $}}578 ; WAVE32-NEXT: bb.2:579 ; WAVE32-NEXT: successors: %bb.3(0x80000000)580 ; WAVE32-NEXT: {{ $}}581 ; WAVE32-NEXT: S_NOP 1582 ; WAVE32-NEXT: {{ $}}583 ; WAVE32-NEXT: bb.3:584 ; WAVE32-NEXT: S_NOP 2585 bb.0:586 successors: %bb.1587 liveins: $vgpr0, $vgpr1588 %0:_(s32) = COPY $vgpr0589 %1:_(s32) = COPY $vgpr1590 %2:_(s1) = G_ICMP intpred(ne), %0, %1591 %3:_(s1), %4:_(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.if), %2592 %5:_(s1) = G_CONSTANT i1 true593 %6:_(s1) = G_XOR %3, %5594 G_BRCOND %6, %bb.2595 G_BR %bb.3596 597 bb.1:598 S_NOP 0599 600 bb.2:601 S_NOP 1602 603 bb.3:604 S_NOP 2605...606 607---608name: brcond_si_loop_brcond_negated609tracksRegLiveness: true610body: |611 ; WAVE64-LABEL: name: brcond_si_loop_brcond_negated612 ; WAVE64: bb.0:613 ; WAVE64-NEXT: successors: %bb.1(0x80000000)614 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1615 ; WAVE64-NEXT: {{ $}}616 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0617 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1618 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1619 ; WAVE64-NEXT: {{ $}}620 ; WAVE64-NEXT: bb.1:621 ; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)622 ; WAVE64-NEXT: {{ $}}623 ; WAVE64-NEXT: S_NOP 0624 ; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec625 ; WAVE64-NEXT: G_BR %bb.2626 ; WAVE64-NEXT: {{ $}}627 ; WAVE64-NEXT: bb.2:628 ; WAVE64-NEXT: S_NOP 0629 ; WAVE32-LABEL: name: brcond_si_loop_brcond_negated630 ; WAVE32: bb.0:631 ; WAVE32-NEXT: successors: %bb.1(0x80000000)632 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1633 ; WAVE32-NEXT: {{ $}}634 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0635 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1636 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1637 ; WAVE32-NEXT: {{ $}}638 ; WAVE32-NEXT: bb.1:639 ; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)640 ; WAVE32-NEXT: {{ $}}641 ; WAVE32-NEXT: S_NOP 0642 ; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec643 ; WAVE32-NEXT: G_BR %bb.2644 ; WAVE32-NEXT: {{ $}}645 ; WAVE32-NEXT: bb.2:646 ; WAVE32-NEXT: S_NOP 0647 bb.0:648 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1649 %0:_(s32) = COPY $vgpr0650 %1:_(s32) = COPY $vgpr1651 %2:_(s64) = COPY $sgpr0_sgpr1652 653 bb.1:654 successors: %bb.1, %bb.2655 S_NOP 0656 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2657 %4:_(s1) = G_CONSTANT i1 true658 %5:_(s1) = G_XOR %3, %4659 G_BRCOND %5, %bb.1660 661 bb.2:662 S_NOP 0663...664 665---666name: brcond_si_loop_brcond_br_negated667tracksRegLiveness: true668body: |669 ; WAVE64-LABEL: name: brcond_si_loop_brcond_br_negated670 ; WAVE64: bb.0:671 ; WAVE64-NEXT: successors: %bb.1(0x80000000)672 ; WAVE64-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1673 ; WAVE64-NEXT: {{ $}}674 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0675 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1676 ; WAVE64-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec(s64) = COPY $sgpr0_sgpr1677 ; WAVE64-NEXT: {{ $}}678 ; WAVE64-NEXT: bb.1:679 ; WAVE64-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)680 ; WAVE64-NEXT: {{ $}}681 ; WAVE64-NEXT: S_NOP 0682 ; WAVE64-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec683 ; WAVE64-NEXT: G_BR %bb.1684 ; WAVE64-NEXT: {{ $}}685 ; WAVE64-NEXT: bb.2:686 ; WAVE64-NEXT: S_NOP 0687 ; WAVE32-LABEL: name: brcond_si_loop_brcond_br_negated688 ; WAVE32: bb.0:689 ; WAVE32-NEXT: successors: %bb.1(0x80000000)690 ; WAVE32-NEXT: liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1691 ; WAVE32-NEXT: {{ $}}692 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0693 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1694 ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec(s64) = COPY $sgpr0_sgpr1695 ; WAVE32-NEXT: {{ $}}696 ; WAVE32-NEXT: bb.1:697 ; WAVE32-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)698 ; WAVE32-NEXT: {{ $}}699 ; WAVE32-NEXT: S_NOP 0700 ; WAVE32-NEXT: SI_LOOP [[COPY2]](s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec701 ; WAVE32-NEXT: G_BR %bb.1702 ; WAVE32-NEXT: {{ $}}703 ; WAVE32-NEXT: bb.2:704 ; WAVE32-NEXT: S_NOP 0705 bb.0:706 liveins: $vgpr0, $vgpr1, $sgpr0_sgpr1707 %0:_(s32) = COPY $vgpr0708 %1:_(s32) = COPY $vgpr1709 %2:_(s64) = COPY $sgpr0_sgpr1710 711 bb.1:712 successors: %bb.1, %bb.2713 S_NOP 0714 %3:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), %2715 %4:_(s1) = G_CONSTANT i1 true716 %5:_(s1) = G_XOR %3, %4717 G_BRCOND %5, %bb.2718 G_BR %bb.1719 720 bb.2:721 S_NOP 0722...723