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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s3 4---5name: ctlz_zero_undef_s32_s326 7body: |8 bb.0:9 liveins: $vgpr010 ; CHECK-LABEL: name: ctlz_zero_undef_s32_s3211 ; CHECK: liveins: $vgpr012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr014 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)15 ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)16 %0:_(s32) = COPY $vgpr017 %1:_(s32) = G_CTLZ_ZERO_UNDEF %018 $vgpr0 = COPY %119...20 21---22name: ctlz_zero_undef_s32_s6423 24body: |25 bb.0:26 liveins: $vgpr0_vgpr127 ; CHECK-LABEL: name: ctlz_zero_undef_s32_s6428 ; CHECK: liveins: $vgpr0_vgpr129 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr131 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)32 ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)33 %0:_(s64) = COPY $vgpr0_vgpr134 %1:_(s32) = G_CTLZ_ZERO_UNDEF %035 $vgpr0 = COPY %136...37 38---39name: ctlz_zero_undef_s64_s6440 41body: |42 bb.0:43 liveins: $vgpr0_vgpr144 ; CHECK-LABEL: name: ctlz_zero_undef_s64_s6445 ; CHECK: liveins: $vgpr0_vgpr146 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr148 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)49 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)50 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)51 %0:_(s64) = COPY $vgpr0_vgpr152 %1:_(s64) = G_CTLZ_ZERO_UNDEF %053 $vgpr0_vgpr1 = COPY %154...55 56---57name: ctlz_zero_undef_s16_s3258 59body: |60 bb.0:61 liveins: $vgpr062 ; CHECK-LABEL: name: ctlz_zero_undef_s16_s3263 ; CHECK: liveins: $vgpr064 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr066 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)67 ; CHECK-NEXT: $vgpr0 = COPY [[CTLZ_ZERO_UNDEF]](s32)68 %0:_(s32) = COPY $vgpr069 %1:_(s16) = G_CTLZ_ZERO_UNDEF %070 %2:_(s32) = G_ZEXT %171 $vgpr0 = COPY %272...73 74---75name: ctlz_zero_undef_s16_s1676 77body: |78 bb.0:79 liveins: $vgpr080 ; CHECK-LABEL: name: ctlz_zero_undef_s16_s1681 ; CHECK: liveins: $vgpr082 ; CHECK-NEXT: {{ $}}83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr084 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1685 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)86 ; CHECK-NEXT: [[AMDGPU_FFBH_U32:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[SHL]](s32)87 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553588 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMDGPU_FFBH_U32]], [[C1]]89 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)90 %0:_(s32) = COPY $vgpr091 %1:_(s16) = G_TRUNC %092 %2:_(s16) = G_CTLZ_ZERO_UNDEF %193 %3:_(s32) = G_ZEXT %294 $vgpr0 = COPY %395...96 97---98name: ctlz_zero_undef_v2s32_v2s3299 100body: |101 bb.0:102 liveins: $vgpr0_vgpr1103 ; CHECK-LABEL: name: ctlz_zero_undef_v2s32_v2s32104 ; CHECK: liveins: $vgpr0_vgpr1105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1107 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)108 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s32)109 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)110 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ_ZERO_UNDEF]](s32), [[CTLZ_ZERO_UNDEF1]](s32)111 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)112 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1113 %1:_(<2 x s32>) = G_CTLZ_ZERO_UNDEF %0114 $vgpr0_vgpr1 = COPY %1115...116 117---118name: ctlz_zero_undef_v2s32_v2s64119 120body: |121 bb.0:122 liveins: $vgpr0_vgpr1_vgpr2_vgpr3123 ; CHECK-LABEL: name: ctlz_zero_undef_v2s32_v2s64124 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3127 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)128 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s64)129 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV1]](s64)130 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ_ZERO_UNDEF]](s32), [[CTLZ_ZERO_UNDEF1]](s32)131 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)132 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3133 %1:_(<2 x s32>) = G_CTLZ_ZERO_UNDEF %0134 $vgpr0_vgpr1 = COPY %1135...136 137---138name: ctlz_zero_undef_v2s16_v2s16139 140body: |141 bb.0:142 liveins: $vgpr0143 ; CHECK-LABEL: name: ctlz_zero_undef_v2s16_v2s16144 ; CHECK: liveins: $vgpr0145 ; CHECK-NEXT: {{ $}}146 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0147 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)148 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16149 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)150 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)151 ; CHECK-NEXT: [[AMDGPU_FFBH_U32:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[SHL]](s32)152 ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)153 ; CHECK-NEXT: [[AMDGPU_FFBH_U321:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[SHL2]](s32)154 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535155 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMDGPU_FFBH_U32]], [[C1]]156 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AMDGPU_FFBH_U321]], [[C1]]157 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)158 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]159 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)160 ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)161 %0:_(<2 x s16>) = COPY $vgpr0162 %1:_(<2 x s16>) = G_CTLZ_ZERO_UNDEF %0163 $vgpr0 = COPY %1164...165 166---167name: ctlz_zero_undef_s7_s7168 169body: |170 bb.0:171 liveins: $vgpr0172 173 ; CHECK-LABEL: name: ctlz_zero_undef_s7_s7174 ; CHECK: liveins: $vgpr0175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0177 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25178 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)179 ; CHECK-NEXT: [[FFBH:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[SHL]](s32)180 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127181 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[FFBH]], [[C1]]182 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)183 %0:_(s32) = COPY $vgpr0184 %1:_(s7) = G_TRUNC %0185 %2:_(s7) = G_CTLZ_ZERO_UNDEF %1186 %3:_(s32) = G_ZEXT %2187 $vgpr0 = COPY %3188...189 190---191name: ctlz_zero_undef_s33_s33192 193body: |194 bb.0:195 liveins: $vgpr0_vgpr1196 197 ; CHECK-LABEL: name: ctlz_zero_undef_s33_s33198 ; CHECK: liveins: $vgpr0_vgpr1199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591202 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]203 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31204 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[C1]](s32)205 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[SHL]](s64)206 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)207 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)208 %0:_(s64) = COPY $vgpr0_vgpr1209 %1:_(s33) = G_TRUNC %0210 %2:_(s33) = G_CTLZ_ZERO_UNDEF %1211 %3:_(s64) = G_ANYEXT %2212 $vgpr0_vgpr1 = COPY %3213...214