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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s3 4---5name: ctlz_s32_s326 7body: |8 bb.0:9 liveins: $vgpr010 ; CHECK-LABEL: name: ctlz_s32_s3211 ; CHECK: liveins: $vgpr012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr014 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)15 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3216 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]17 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)18 %0:_(s32) = COPY $vgpr019 %1:_(s32) = G_CTLZ %020 $vgpr0 = COPY %121...22 23---24name: ctlz_s32_s6425 26body: |27 bb.0:28 liveins: $vgpr0_vgpr129 ; CHECK-LABEL: name: ctlz_s32_s6430 ; CHECK: liveins: $vgpr0_vgpr131 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr133 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64)34 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6435 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]36 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)37 %0:_(s64) = COPY $vgpr0_vgpr138 %1:_(s32) = G_CTLZ %039 $vgpr0 = COPY %140...41 42---43name: ctlz_s64_s6444 45body: |46 bb.0:47 liveins: $vgpr0_vgpr148 ; CHECK-LABEL: name: ctlz_s64_s6449 ; CHECK: liveins: $vgpr0_vgpr150 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr152 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s64)53 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6454 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]55 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UMIN]](s32)56 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)57 %0:_(s64) = COPY $vgpr0_vgpr158 %1:_(s64) = G_CTLZ %059 $vgpr0_vgpr1 = COPY %160...61 62---63name: ctlz_s16_s3264 65body: |66 bb.0:67 liveins: $vgpr068 ; CHECK-LABEL: name: ctlz_s16_s3269 ; CHECK: liveins: $vgpr070 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr072 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[COPY]](s32)73 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3274 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]75 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)76 %0:_(s32) = COPY $vgpr077 %1:_(s16) = G_CTLZ %078 %2:_(s32) = G_ZEXT %179 $vgpr0 = COPY %280...81 82---83name: ctlz_s16_s1684 85body: |86 bb.0:87 liveins: $vgpr088 ; CHECK-LABEL: name: ctlz_s16_s1689 ; CHECK: liveins: $vgpr090 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr092 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553593 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]94 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)95 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3296 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]97 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1698 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]99 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)100 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]101 ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)102 %0:_(s32) = COPY $vgpr0103 %1:_(s16) = G_TRUNC %0104 %2:_(s16) = G_CTLZ %1105 %3:_(s32) = G_ZEXT %2106 $vgpr0 = COPY %3107...108 109---110name: ctlz_v2s32_v2s32111 112body: |113 bb.0:114 liveins: $vgpr0_vgpr1115 ; CHECK-LABEL: name: ctlz_v2s32_v2s32116 ; CHECK: liveins: $vgpr0_vgpr1117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1119 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)120 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV]](s32)121 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32122 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]123 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s32)124 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C]]125 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)126 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)127 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1128 %1:_(<2 x s32>) = G_CTLZ %0129 $vgpr0_vgpr1 = COPY %1130...131 132---133name: ctlz_v2s32_v2s64134 135body: |136 bb.0:137 liveins: $vgpr0_vgpr1_vgpr2_vgpr3138 ; CHECK-LABEL: name: ctlz_v2s32_v2s64139 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3142 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)143 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV]](s64)144 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64145 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]146 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s64)147 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C]]148 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)149 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)150 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3151 %1:_(<2 x s32>) = G_CTLZ %0152 $vgpr0_vgpr1 = COPY %1153...154 155---156name: ctlz_v2s16_v2s16157 158body: |159 bb.0:160 liveins: $vgpr0161 ; CHECK-LABEL: name: ctlz_v2s16_v2s16162 ; CHECK: liveins: $vgpr0163 ; CHECK-NEXT: {{ $}}164 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0165 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)166 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16167 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)168 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535169 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]170 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)171 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32172 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C2]]173 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C]]174 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)175 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[LSHR]](s32)176 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C2]]177 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMIN1]], [[C]]178 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)179 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]180 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]181 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)182 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]183 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)184 ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)185 %0:_(<2 x s16>) = COPY $vgpr0186 %1:_(<2 x s16>) = G_CTLZ %0187 $vgpr0 = COPY %1188...189 190---191name: ctlz_s7_s7192 193body: |194 bb.0:195 liveins: $vgpr0196 197 ; CHECK-LABEL: name: ctlz_s7_s7198 ; CHECK: liveins: $vgpr0199 ; CHECK-NEXT: {{ $}}200 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127202 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]203 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)204 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32205 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]206 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25207 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]208 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)209 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]210 ; CHECK-NEXT: $vgpr0 = COPY [[AND1]](s32)211 %0:_(s32) = COPY $vgpr0212 %1:_(s7) = G_TRUNC %0213 %2:_(s7) = G_CTLZ %1214 %3:_(s32) = G_ZEXT %2215 $vgpr0 = COPY %3216...217 218---219name: ctlz_s33_s33220 221body: |222 bb.0:223 liveins: $vgpr0_vgpr1224 225 ; CHECK-LABEL: name: ctlz_s33_s33226 ; CHECK: liveins: $vgpr0_vgpr1227 ; CHECK-NEXT: {{ $}}228 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1229 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591230 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]231 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s64)232 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64233 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]234 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 31235 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)236 ; CHECK-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UMIN]], [[UV]]237 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[USUBO]](s32)238 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)239 %0:_(s64) = COPY $vgpr0_vgpr1240 %1:_(s33) = G_TRUNC %0241 %2:_(s33) = G_CTLZ %1242 %3:_(s64) = G_ANYEXT %2243 $vgpr0_vgpr1 = COPY %3244...245 246# ---247# name: ctlz_v2s7_v2s7248 249# body: |250# bb.0:251# liveins: $vgpr0252# %0:_(<2 x s32>) = COPY $vgpr0_vgpr1253# %1:_(<2 x s7>) = G_TRUNC %0254# %2:_(<2 x s7>) = G_CTLZ %1255# %3:_(<2 x s32>) = G_ANYEXT %2256# $vgpr0_vgpr1 = COPY %3257# ...258