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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s3 4---5name: cttz_s32_s326 7body: |8 bb.0:9 liveins: $vgpr010 ; CHECK-LABEL: name: cttz_s32_s3211 ; CHECK: liveins: $vgpr012 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr014 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s32)15 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3216 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]17 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)18 %0:_(s32) = COPY $vgpr019 %1:_(s32) = G_CTTZ %020 $vgpr0 = COPY %121...22 23---24name: cttz_s32_s6425 26body: |27 bb.0:28 liveins: $vgpr0_vgpr129 ; CHECK-LABEL: name: cttz_s32_s6430 ; CHECK: liveins: $vgpr0_vgpr131 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr133 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s64)34 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6435 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]36 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)37 %0:_(s64) = COPY $vgpr0_vgpr138 %1:_(s32) = G_CTTZ %039 $vgpr0 = COPY %140...41 42---43name: cttz_s64_s6444 45body: |46 bb.0:47 liveins: $vgpr0_vgpr148 ; CHECK-LABEL: name: cttz_s64_s6449 ; CHECK: liveins: $vgpr0_vgpr150 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr152 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s64)53 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6454 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]55 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UMIN]](s32)56 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)57 %0:_(s64) = COPY $vgpr0_vgpr158 %1:_(s64) = G_CTTZ %059 $vgpr0_vgpr1 = COPY %160...61 62---63name: cttz_s16_s3264 65body: |66 bb.0:67 liveins: $vgpr068 ; CHECK-LABEL: name: cttz_s16_s3269 ; CHECK: liveins: $vgpr070 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr072 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[COPY]](s32)73 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3274 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]75 ; CHECK-NEXT: $vgpr0 = COPY [[UMIN]](s32)76 %0:_(s32) = COPY $vgpr077 %1:_(s16) = G_CTTZ %078 %2:_(s32) = G_ZEXT %179 $vgpr0 = COPY %280...81 82---83name: cttz_s16_s1684 85body: |86 bb.0:87 liveins: $vgpr088 ; CHECK-LABEL: name: cttz_s16_s1689 ; CHECK: liveins: $vgpr090 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr092 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553693 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]94 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)95 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)96 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553597 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]98 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)99 %0:_(s32) = COPY $vgpr0100 %1:_(s16) = G_TRUNC %0101 %2:_(s16) = G_CTTZ %1102 %3:_(s32) = G_ZEXT %2103 $vgpr0 = COPY %3104...105 106---107name: cttz_v2s32_v2s32108 109body: |110 bb.0:111 liveins: $vgpr0_vgpr1112 ; CHECK-LABEL: name: cttz_v2s32_v2s32113 ; CHECK: liveins: $vgpr0_vgpr1114 ; CHECK-NEXT: {{ $}}115 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1116 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)117 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV]](s32)118 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32119 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]120 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s32)121 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_1]], [[C]]122 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)123 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)124 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1125 %1:_(<2 x s32>) = G_CTTZ %0126 $vgpr0_vgpr1 = COPY %1127...128 129---130name: cttz_v2s32_v2s64131 132body: |133 bb.0:134 liveins: $vgpr0_vgpr1_vgpr2_vgpr3135 ; CHECK-LABEL: name: cttz_v2s32_v2s64136 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3139 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)140 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV]](s64)141 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64142 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]143 ; CHECK-NEXT: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s64)144 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_1]], [[C]]145 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32)146 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)147 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3148 %1:_(<2 x s32>) = G_CTTZ %0149 $vgpr0_vgpr1 = COPY %1150...151 152---153name: cttz_v2s16_v2s16154 155body: |156 bb.0:157 liveins: $vgpr0158 ; CHECK-LABEL: name: cttz_v2s16_v2s16159 ; CHECK: liveins: $vgpr0160 ; CHECK-NEXT: {{ $}}161 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0162 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)163 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16164 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)165 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536166 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[BITCAST]], [[C1]]167 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)168 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)169 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[C1]]170 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)171 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)172 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535173 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]174 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]175 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)176 ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]177 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)178 ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)179 %0:_(<2 x s16>) = COPY $vgpr0180 %1:_(<2 x s16>) = G_CTTZ %0181 $vgpr0 = COPY %1182...183 184---185name: cttz_s7_s7186 187body: |188 bb.0:189 liveins: $vgpr0190 191 ; CHECK-LABEL: name: cttz_s7_s7192 ; CHECK: liveins: $vgpr0193 ; CHECK-NEXT: {{ $}}194 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0195 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128196 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]197 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)198 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)199 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127200 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]201 ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)202 %0:_(s32) = COPY $vgpr0203 %1:_(s7) = G_TRUNC %0204 %2:_(s7) = G_CTTZ %1205 %3:_(s32) = G_ZEXT %2206 $vgpr0 = COPY %3207...208 209---210name: cttz_s33_s33211 212body: |213 bb.0:214 liveins: $vgpr0_vgpr1215 216 ; CHECK-LABEL: name: cttz_s33_s33217 ; CHECK: liveins: $vgpr0_vgpr1218 ; CHECK-NEXT: {{ $}}219 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1220 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592221 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]222 ; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s64)223 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)224 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)225 %0:_(s64) = COPY $vgpr0_vgpr1226 %1:_(s33) = G_TRUNC %0227 %2:_(s33) = G_CTTZ %1228 %3:_(s64) = G_ANYEXT %2229 $vgpr0_vgpr1 = COPY %3230...231