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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s3 4---5name: test_amdgcn_fdiv_fast6body: |7 bb.0:8 liveins: $vgpr0, $vgpr19 10 ; CHECK-LABEL: name: test_amdgcn_fdiv_fast11 ; CHECK: liveins: $vgpr0, $vgpr112 ; CHECK-NEXT: {{ $}}13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr014 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr115 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY1]]16 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x45F000000000000017 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF000000000000018 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0019 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]20 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]21 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY1]], [[SELECT]]22 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FMUL]](s32)23 ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[INT]]24 ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[SELECT]], [[FMUL1]]25 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL2]](s32)26 %0:_(s32) = COPY $vgpr027 %1:_(s32) = COPY $vgpr128 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %129 $vgpr0 = COPY %230...31 32---33name: test_amdgcn_fdiv_fast_propagate_flags34body: |35 bb.0:36 liveins: $vgpr0, $vgpr137 38 ; CHECK-LABEL: name: test_amdgcn_fdiv_fast_propagate_flags39 ; CHECK: liveins: $vgpr0, $vgpr140 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr042 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr143 ; CHECK-NEXT: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[COPY1]]44 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x45F000000000000045 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3DF000000000000046 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+0047 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]48 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]49 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY1]], [[SELECT]]50 ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FMUL]](s32)51 ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY]], [[INT]]52 ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = nsz G_FMUL [[SELECT]], [[FMUL1]]53 ; CHECK-NEXT: $vgpr0 = COPY [[FMUL2]](s32)54 %0:_(s32) = COPY $vgpr055 %1:_(s32) = COPY $vgpr156 %2:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %157 $vgpr0 = COPY %258...59